summaryrefslogtreecommitdiff
path: root/src/cpu
AgeCommit message (Expand)Author
2015-08-14ruby: replace Address by AddrNilay Vaish
2015-08-11ruby: drop some redundant includesNilay Vaish
2015-08-07base: Declare a type for context IDsAndreas Sandberg
2015-07-20cpu: Fixed a bug on where to fetch the next instruction fromDavid Hashe
2015-07-31cpu: Update debug message from Fetch1 isDrained() in MinorAndreas Sandberg
2015-07-31cpu: Fix Minor drain issues when switched outAndreas Sandberg
2015-07-30cpu: Only activate thread 0 in Minor if the CPU is activeAndreas Sandberg
2015-07-30cpu: Fix drain issues in the Minor CPUAndreas Sandberg
2015-07-30cpu: Fix issue identified by UBSanAndreas Hansson
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-26cpu: o3: slight correction to identation in rename_impl.hhNilay Vaish
2015-07-10ruby: replace global g_abs_controls with per-RubySystem varBrandon Potter
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-07-04o3: correct the number of cc registers in rename mapNilay Vaish
2015-06-01kvm, arm: Add support for aarch64Andreas Sandberg
2015-06-01kvm, arm, dev: Add an in-kernel GIC implementationAndreas Sandberg
2015-06-01kvm: Handle inst events at the current instruction countAndreas Sandberg
2015-06-01kvm, arm: Move ARM-specific files to arch/arm/kvm/Andreas Sandberg
2015-05-26cpu: Fix a bug in counting issued instructions in MinorCPUAndrew Bardsley
2015-05-23kvm: Fix dumping code for large registersAndreas Sandberg
2015-05-23kvm, x86: Guard x86-specific APIs in KvmVMAndreas Sandberg
2015-05-15misc: Appease gcc 5.1Andreas Hansson
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2015-05-05mem: Snoop into caches on uncacheable accessesAndreas Hansson
2015-05-05cpu: Work around gcc 4.9 issues with Num_OpClassesAndreas Hansson
2015-04-29cpu: o3: replace issueLatency with bool pipelinedNilay Vaish
2015-04-29cpu: o3: single cycle default div microop latency on x86Nilay Vaish
2015-04-22cpu: remove conditional check (count > 0) on o3 IQ squashesBrandon Potter
2015-04-20cpu: Remove the InOrderCPU from the treeAndreas Hansson
2015-04-14config, cpu: fix progress interval for switched CPUsMalek Musleh
2015-04-13cpu: re-organizes the branch predictor structure.Dibakar Gope
2015-04-03cpu: fix system total instructions accountingNikos Nikoleris
2015-03-26cpu: Fix InstPBTrace inheritanceAndreas Hansson
2015-03-23mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMWSteve Reinhardt
2015-03-19cpu: Fix TrafficGen message formatWendy Elsasser
2015-02-11mem: restructure Packet cmd initialization a bit moreSteve Reinhardt
2015-03-09cpu: o3: another assert instead of checkNilay Vaish
2015-03-09cpu: o3: Remove unused code in iew, add assert instead.Nilay Vaish
2015-03-09cpu: o3: commit: mark pipeline delay variable as constsNilay Vaish
2015-03-09cpu: o3: remove unused stat variables.Nilay Vaish
2015-03-09cpu: o3: combine if with same conditionNilay Vaish
2015-03-09cpu: o3: remove member variable squashCounterNilay Vaish
2015-03-09cpu: o3: remove unused function annotateMemoryUnits()Nilay Vaish
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-03-02arm: Share a port for the two table walker objectsAndreas Hansson
2015-03-02cpu: o3 register renaming request handling improvedRekai
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 01:06:40 +0000