gem5 - gem5

Age	Commit message (Expand)	Author
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-10-15	Regression: Use CPU clock and 32-byte width for L1-L2 bus	Andreas Hansson
2012-09-25	O3: Pack the comm structures a bit better to reduce their size.	Ali Saidi
2012-09-25	ARM: Squash outstanding walks when instructions are squashed.	Ali Saidi
2012-09-25	sim: Move CPU-specific methods from SimObject to the BaseCPU class	Andreas Sandberg
2012-09-25	CPU: Add abandoned instructions to O3 Pipe Viewer	Djordje Kovacevic
2012-09-21	TrafficGen: Add a basic traffic generator	Andreas Hansson
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-12	Base CPU: Initialize profileEvent to NULL	Joel Hestness
2012-09-12	stats: remove duplicate instruction stats from the commit stage	Anthony Gutierrez
2012-09-11	Ruby: Use uint8_t instead of uint8 everywhere	Nilay Vaish
2012-09-07	O3: Get rid of incorrect assert in RAS.	Ali Saidi
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-28	Port: Stricter port bind/unbind semantics	Andreas Hansson
2012-08-28	Checker: Fix checker CPU ports	Andreas Hansson
2012-08-27	Ruby: Remove RubyEventQueue	Nilay Vaish
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-21	CPU: Remove overloaded function_trace_start parameter	Andreas Hansson
2012-08-21	Clock: Make Tick unsigned and remove UTick	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-08-06	process: add progName() virtual function	Steve Reinhardt
2012-07-27	checker: make checker cpu id match its host's cpu id	Anthony Gutierrez
2012-07-10	ruby: remove the cpu assumptions for the random tester	Brad Beckmann
2012-07-10	cpu: added assertions to ensure the correct proxies are used	Brad Beckmann
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Port: Move retry from port base class to Master/SlavePort	Andreas Hansson
2012-07-09	Fix: Address a few benign memory leaks	Andreas Hansson
2012-06-29	O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.	Nathanael Premillieu
2012-06-08	Timing CPU: Remove a redundant port pointer	Andreas Hansson
2012-06-05	cpu: Don't init simple and inorder CPUs if they are defered.	Anthony Gutierrez
2012-06-05	ISA: Back-out NoopMachInst as a StaticInstPtr change.	Ali Saidi
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-06-04	ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.	Gabe Black
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-05-30	Packet: Unify the use of PortID in packet and port	Andreas Hansson
2012-05-26	ISA,CPU: Generalize and split out the components of the decode cache.	Gabe Black
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-25	ISA: Make the decode function part of the ISA's decoder.	Gabe Black
2012-05-25	CPU: Simplify the implementation of the decode cache.	Gabe Black
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black
2012-05-10	gem5: fix some iterator use and erase bugs	Ali Saidi
2012-05-10	gem5: fix a number of use after free issues	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-25	MEM: Add the PortId type and a corresponding id field to Port	Andreas Hansson
2012-04-15	CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.	Gabe Black
2012-04-14	Ruby: Use MasterPort base-class pointers where possible	Andreas Hansson