gem5 - gem5

Age	Commit message (Collapse)	Author
2009-11-04	build: fix compile problems pointed out by gcc 4.4	Nathan Binkert

2009-11-04	o3: get rid of unused physmem pointer	Steve Reinhardt

2009-10-27	POWER: Add support for the Power ISA	Timothy M. Jones
	This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06.
2009-10-17	ISA: Fix compilation.	Gabe Black

2009-10-15	fixed MC146818 checkpointing bug and added isa serialization calls to ↵	Brad Beckmann
	simple_thread
2009-10-01	inorder-debug: print out workload	Korey Sewell

2009-09-29	commit Soumyaroop's bug catch about max_insts_all_threads	Lisa Hsu

2009-09-26	O3: Add flag to control whether faulting instructions are traced.	Steve Reinhardt
	When enabled, faulting instructions appear in the trace twice (once when they fault and again when they're re-executed). This flag is set by the Exec compound flag for backwards compatibility.
2009-09-26	O3: Mark fetch stage as active if it faults.	Steve Reinhardt
	Otherwise if the rest of the pipeline is idle then fault will never propagate to commit to be handled, causing CPU to deadlock.
2009-09-25	inorder-debug: fix cpu tick debug message	Korey Sewell

2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert

2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
	Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-17	inorder-mdu: multiplier latency fix	Korey Sewell
	mdu was workign incorrectly for 4+ latency due to incorrectly assuming multiply was finished the next stage
2009-09-16	inorder-smt: remove hardcoded values	Soumyaroop Roy
	allows for the 2T hello world example to work in inorder model
2009-09-15	inorder-alpha-fs: edit inorder model to compile FS mode	Korey Sewell

2009-09-01	SCons fix to always make MemTest object	Polina Dudnik

2009-08-23	Atomic CPU: Respect the NO_ACCESS request flag.	Gabe Black

2009-08-01	Fix setting of INST_FETCH flag for O3 CPU.	Steve Reinhardt
	It's still broken in inorder. Also enhance DPRINTFs in cache and physical memory so we can see more easily whether it's getting set or not.
2009-07-29	Simple CPU: Make the simple CPU handle the IntRegs trace flag.	Gabe Black

2009-07-27	ARM: Make native trace print out what instruction caused an error.	Gabe Black

2009-07-25	o3-smt: enforce numThreads parameter for SMT SE mode	Korey Sewell

2009-07-19	CPU: Separate out native trace into ISA (in)dependent code and SimObjects.	Gabe Black
	--HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-08	Get rid of the unused get(Data\|Inst)Asid and (inst\|data)Asid functions.	Gabe Black

2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
	This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08	Registers: Eliminate the ISA defined RegFile class.	Gabe Black

2009-07-08	Registers: Move the PCs out of the ISAs and into the CPUs.	Gabe Black

2009-07-08	ARM, Simple CPU: Fix an index and add assert checks.	Gabe Black

2009-07-08	Registers: Eliminate the ISA defined integer register file.	Gabe Black

2009-07-08	Registers: Eliminate the ISA defined floating point register file.	Gabe Black

2009-07-08	Registers: Get rid of the float register width parameter.	Gabe Black

2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
	This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert

2009-06-04	move: put predictor includes and cc files into the same place	Nathan Binkert
	--HG-- rename : src/cpu/2bit_local_pred.cc => src/cpu/pred/2bit_local.cc rename : src/cpu/o3/2bit_local_pred.hh => src/cpu/pred/2bit_local.hh rename : src/cpu/btb.cc => src/cpu/pred/btb.cc rename : src/cpu/o3/btb.hh => src/cpu/pred/btb.hh rename : src/cpu/ras.cc => src/cpu/pred/ras.cc rename : src/cpu/o3/ras.hh => src/cpu/pred/ras.hh rename : src/cpu/tournament_pred.cc => src/cpu/pred/tournament.cc rename : src/cpu/o3/tournament_pred.hh => src/cpu/pred/tournament.hh
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert

2009-05-17	includes: sort includes again	Nathan Binkert

2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
	--HG-- rename : src/sim/host.hh => src/base/types.hh
2009-05-12	cpus: add InOrderCPU to default build	Korey Sewell
	regressions need this so they build the model
2009-05-12	inorder-resources: delete events	Korey Sewell
	make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor
2009-05-12	inorder-tlb-cunit: merge the TLB as implicit to any memory access	Korey Sewell
	TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * *
2009-05-12	inorder-tlb: squash insts in TLB correctly	Korey Sewell
	TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly * * *
2009-05-12	inorder-faults: ignore unalign translation faults for prefetches	Korey Sewell

2009-05-12	inorder-stc: update interface to handle store conditionals	Korey Sewell

2009-05-12	inorder-float: Fix storage of FP results	Korey Sewell
	inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from the actual floating point register file, the model can figure out what it needs to store
2009-05-12	inorder-fetch: update model to use predecoder	Korey Sewell

2009-05-12	inorder-mem: clean up allocation/deletion of requests/packets	Korey Sewell
	* * *
2009-05-12	inorder-mem: skeleton support for prefetch/writehints	Korey Sewell

2009-05-12	inorder-o3: allow both to compile together	Korey Sewell
	allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
2009-05-12	inorder-unified-tlb: use unified TLB instead of old TLB model	Korey Sewell

2009-05-12	inorder-miscregs: Fix indexing for misc. reg operands and update ↵	Korey Sewell
	result-types for better tracing of these types of values
2009-05-12	inorder/alpha-isa: create eaComp object visible to StaticInst through ISA	Korey Sewell
	Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * *