gem5 - gem5

Age	Commit message (Expand)	Author
2015-07-31	cpu: Fix Minor drain issues when switched out	Andreas Sandberg
2015-07-30	cpu: Only activate thread 0 in Minor if the CPU is active	Andreas Sandberg
2015-07-30	cpu: Fix drain issues in the Minor CPU	Andreas Sandberg
2015-07-30	cpu: Fix issue identified by UBSan	Andreas Hansson
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2015-07-26	cpu: o3: slight correction to identation in rename_impl.hh	Nilay Vaish
2015-07-10	ruby: replace global g_abs_controls with per-RubySystem var	Brandon Potter
2015-07-07	sim: Refactor and simplify the drain API	Andreas Sandberg
2015-07-07	sim: Make the drain state a global typed enum	Andreas Sandberg
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-07-04	o3: correct the number of cc registers in rename map	Nilay Vaish
2015-06-01	kvm, arm: Add support for aarch64	Andreas Sandberg
2015-06-01	kvm, arm, dev: Add an in-kernel GIC implementation	Andreas Sandberg
2015-06-01	kvm: Handle inst events at the current instruction count	Andreas Sandberg
2015-06-01	kvm, arm: Move ARM-specific files to arch/arm/kvm/	Andreas Sandberg
2015-05-26	cpu: Fix a bug in counting issued instructions in MinorCPU	Andrew Bardsley
2015-05-23	kvm: Fix dumping code for large registers	Andreas Sandberg
2015-05-23	kvm, x86: Guard x86-specific APIs in KvmVM	Andreas Sandberg
2015-05-15	misc: Appease gcc 5.1	Andreas Hansson
2015-05-05	mem, cpu: Add a separate flag for strictly ordered memory	Andreas Sandberg
2015-05-05	mem: Snoop into caches on uncacheable accesses	Andreas Hansson
2015-05-05	cpu: Work around gcc 4.9 issues with Num_OpClasses	Andreas Hansson
2015-04-29	cpu: o3: replace issueLatency with bool pipelined	Nilay Vaish
2015-04-29	cpu: o3: single cycle default div microop latency on x86	Nilay Vaish
2015-04-22	cpu: remove conditional check (count > 0) on o3 IQ squashes	Brandon Potter
2015-04-20	cpu: Remove the InOrderCPU from the tree	Andreas Hansson
2015-04-14	config, cpu: fix progress interval for switched CPUs	Malek Musleh
2015-04-13	cpu: re-organizes the branch predictor structure.	Dibakar Gope
2015-04-03	cpu: fix system total instructions accounting	Nikos Nikoleris
2015-03-26	cpu: Fix InstPBTrace inheritance	Andreas Hansson
2015-03-23	mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW	Steve Reinhardt
2015-03-19	cpu: Fix TrafficGen message format	Wendy Elsasser
2015-02-11	mem: restructure Packet cmd initialization a bit more	Steve Reinhardt
2015-03-09	cpu: o3: another assert instead of check	Nilay Vaish
2015-03-09	cpu: o3: Remove unused code in iew, add assert instead.	Nilay Vaish
2015-03-09	cpu: o3: commit: mark pipeline delay variable as consts	Nilay Vaish
2015-03-09	cpu: o3: remove unused stat variables.	Nilay Vaish
2015-03-09	cpu: o3: combine if with same condition	Nilay Vaish
2015-03-09	cpu: o3: remove member variable squashCounter	Nilay Vaish
2015-03-09	cpu: o3: remove unused function annotateMemoryUnits()	Nilay Vaish
2015-03-02	mem: Move crossbar default latencies to subclasses	Andreas Hansson
2015-03-02	arm: Share a port for the two table walker objects	Andreas Hansson
2015-03-02	cpu: o3 register renaming request handling improved	Rekai
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2015-03-02	cpu: Add a PC-value to the traffic generator requests	Stephan Diestelhorst
2015-02-16	cpu: TrafficGen sinks snoops without complaining	Andreas Hansson
2015-02-16	arch: Make readMiscRegNoEffect const throughout	Andreas Hansson
2015-02-16	cpu: add support for outputing a protobuf formatted CPU trace	Ali Saidi
2015-02-11	cpu: Tidy up the MemTest and make false sharing more obvious	Andreas Hansson