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path: root/src/cpu
AgeCommit message (Expand)Author
2019-05-13cpu: Make the indirect predictor into a SimObjectJairo Balart
2019-05-11cpu,mem: Add support for partial loads/stores and wide mem. accessesGiacomo Gabrielli
2019-05-11cpu: Add a memory access predicateGiacomo Gabrielli
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-29cpu: Get rid of the (read|set)RegOtherThread methods.Gabe Black
2019-04-29cpu: Include debug flags regardless of whether the ISA is null.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-24cpu,mem: missing override specifierAndrea Mondelli
2019-04-22cpu: Eliminate the ProxyThreadContext class.Gabe Black
2019-04-10cpu: O3 switchFreeList checking VecElems instead of FloatRegsGiacomo Travaglini
2019-04-05cpu: Correctly account for executed instructions in simple cpusNikos Nikoleris
2019-04-03misc: Removed inconsistency in O3* debug msgsAndrea Mondelli
2019-04-03arch-mips: added missing override specifier (o3)Andrea Mondelli
2019-03-28cpu: Added a probe to notify the address of retired instructionsJavier Bueno
2019-03-27cpu: Fixed the indirect branch predictor GHR handlingPau Cabre
2019-03-23misc: missing override specifierAndrea Mondelli
2019-03-21cpu-kvm: Added informative error messageRyan Gambord
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-14cpu: Refactor of Physical Register implementationAndrea Mondelli
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
2019-02-27misc: Segmentation Fault during O3PipeView executionAndrea Mondelli
2019-02-26cpu: Fix indirect branch history updatesSrikant Bharadwaj
2019-02-22python: Fix param -> int conversion issuesAndreas Sandberg
2019-02-22cpu-o3: Add cache read ports limit to LSQGabor Dozsa
2019-02-22python: Make iterator handling Python 3 compatibleAndreas Sandberg
2019-02-19cpu: Add ISA* getter in Thread interfaceGiacomo Gabrielli
2019-02-15cpu: Fix fast build broken due to unused variableGiacomo Travaglini
2019-02-13cpu: Added 8KB and 64KB TAGE-SC-L branch predictorJavier Bueno
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-08cpu: Proposal for changing the indirect branch predictor interfaceJairo Balart
2019-02-08cpu: support atomic memory request type with AtomicOpFunctorTuan Ta
2019-02-08cpu: fix how branching is handled when a thread is suspended in MinorCPUTuan Ta
2019-02-08cpu: stop scheduling suspended threads in all stages of MinorCPUTuan Ta
2019-02-08sim,cpu: make exit_group halt all threads in a groupTuan Ta
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
2019-02-06cpu: fix how a thread starts up in MinorCPUTuan Ta
2019-02-05misc: added missing override specifierAndrea Mondelli
2019-02-05cpu: Made the Loop Predictor a SimObjectJavier Bueno
2019-02-05cpu: Made TAGE a SimObject that can be used by other predictorsJairo Balart
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
2019-01-25cpu: O3 rename using the flatIndex instead of indexGiacomo Travaglini
2019-01-25cpu: Fix VecElemClass bugs in cpu modelsGiacomo Travaglini
2019-01-25cpu: Add VecElem entries in MinorCPU ScoreboardGiacomo Travaglini
2019-01-24cpu-o3: O3 LSQ GeneralisationRekai Gonzalez-Alberquilla
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