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AgeCommit message (Expand)Author
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2009-09-17inorder-mdu: multiplier latency fixKorey Sewell
2009-09-16inorder-smt: remove hardcoded valuesSoumyaroop Roy
2009-09-15inorder-alpha-fs: edit inorder model to compile FS modeKorey Sewell
2009-09-01SCons fix to always make MemTest objectPolina Dudnik
2009-08-23Atomic CPU: Respect the NO_ACCESS request flag.Gabe Black
2009-08-01Fix setting of INST_FETCH flag for O3 CPU.Steve Reinhardt
2009-07-29Simple CPU: Make the simple CPU handle the IntRegs trace flag.Gabe Black
2009-07-27ARM: Make native trace print out what instruction caused an error.Gabe Black
2009-07-25o3-smt: enforce numThreads parameter for SMT SE modeKorey Sewell
2009-07-19CPU: Separate out native trace into ISA (in)dependent code and SimObjects.Gabe Black
2009-07-08Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.Gabe Black
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
2009-07-08Registers: Eliminate the ISA defined RegFile class.Gabe Black
2009-07-08Registers: Move the PCs out of the ISAs and into the CPUs.Gabe Black
2009-07-08ARM, Simple CPU: Fix an index and add assert checks.Gabe Black
2009-07-08Registers: Eliminate the ISA defined integer register file.Gabe Black
2009-07-08Registers: Eliminate the ISA defined floating point register file.Gabe Black
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-06-04move: put predictor includes and cc files into the same placeNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
2009-05-12cpus: add InOrderCPU to default buildKorey Sewell
2009-05-12inorder-resources: delete eventsKorey Sewell
2009-05-12inorder-tlb-cunit: merge the TLB as implicit to any memory accessKorey Sewell
2009-05-12inorder-tlb: squash insts in TLB correctlyKorey Sewell
2009-05-12inorder-faults: ignore unalign translation faults for prefetchesKorey Sewell
2009-05-12inorder-stc: update interface to handle store conditionalsKorey Sewell
2009-05-12inorder-float: Fix storage of FP resultsKorey Sewell
2009-05-12inorder-fetch: update model to use predecoderKorey Sewell
2009-05-12inorder-mem: clean up allocation/deletion of requests/packetsKorey Sewell
2009-05-12inorder-mem: skeleton support for prefetch/writehintsKorey Sewell
2009-05-12inorder-o3: allow both to compile togetherKorey Sewell
2009-05-12inorder-unified-tlb: use unified TLB instead of old TLB modelKorey Sewell
2009-05-12inorder-miscregs: Fix indexing for misc. reg operands and update result-types...Korey Sewell
2009-05-12inorder/alpha-isa: create eaComp object visible to StaticInst through ISAKorey Sewell
2009-05-12inorder-bpred: edits to handle non-delay-slot ISAsKorey Sewell
2009-05-12inorder-alpha-port: initial inorder support of ALPHAKorey Sewell
2009-05-05cpus: fix cpu progress eventKorey Sewell
2009-04-21arm: Unify the ARM tlb. We forgot about this when we did the rest.Nathan Binkert
2009-04-20request: rename INST_READ to INST_FETCH.Steve Reinhardt
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19CPUs: Make the atomic CPU support locked memory accesses.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-04-19CPU: If the simple CPU is already idle, just return from suspendContext, don'...Gabe Black
2009-04-18o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...Korey Sewell