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2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-17inorder-mdu: multiplier latency fixKorey Sewell
mdu was workign incorrectly for 4+ latency due to incorrectly assuming multiply was finished the next stage
2009-09-16inorder-smt: remove hardcoded valuesSoumyaroop Roy
allows for the 2T hello world example to work in inorder model
2009-09-15inorder-alpha-fs: edit inorder model to compile FS modeKorey Sewell
2009-09-01SCons fix to always make MemTest objectPolina Dudnik
2009-08-23Atomic CPU: Respect the NO_ACCESS request flag.Gabe Black
2009-08-01Fix setting of INST_FETCH flag for O3 CPU.Steve Reinhardt
It's still broken in inorder. Also enhance DPRINTFs in cache and physical memory so we can see more easily whether it's getting set or not.
2009-07-29Simple CPU: Make the simple CPU handle the IntRegs trace flag.Gabe Black
2009-07-27ARM: Make native trace print out what instruction caused an error.Gabe Black
2009-07-25o3-smt: enforce numThreads parameter for SMT SE modeKorey Sewell
2009-07-19CPU: Separate out native trace into ISA (in)dependent code and SimObjects.Gabe Black
--HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-08Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.Gabe Black
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08Registers: Eliminate the ISA defined RegFile class.Gabe Black
2009-07-08Registers: Move the PCs out of the ISAs and into the CPUs.Gabe Black
2009-07-08ARM, Simple CPU: Fix an index and add assert checks.Gabe Black
2009-07-08Registers: Eliminate the ISA defined integer register file.Gabe Black
2009-07-08Registers: Eliminate the ISA defined floating point register file.Gabe Black
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-06-04move: put predictor includes and cc files into the same placeNathan Binkert
--HG-- rename : src/cpu/2bit_local_pred.cc => src/cpu/pred/2bit_local.cc rename : src/cpu/o3/2bit_local_pred.hh => src/cpu/pred/2bit_local.hh rename : src/cpu/btb.cc => src/cpu/pred/btb.cc rename : src/cpu/o3/btb.hh => src/cpu/pred/btb.hh rename : src/cpu/ras.cc => src/cpu/pred/ras.cc rename : src/cpu/o3/ras.hh => src/cpu/pred/ras.hh rename : src/cpu/tournament_pred.cc => src/cpu/pred/tournament.cc rename : src/cpu/o3/tournament_pred.hh => src/cpu/pred/tournament.hh
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
--HG-- rename : src/sim/host.hh => src/base/types.hh
2009-05-12cpus: add InOrderCPU to default buildKorey Sewell
regressions need this so they build the model
2009-05-12inorder-resources: delete eventsKorey Sewell
make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor
2009-05-12inorder-tlb-cunit: merge the TLB as implicit to any memory accessKorey Sewell
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * *
2009-05-12inorder-tlb: squash insts in TLB correctlyKorey Sewell
TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly * * *
2009-05-12inorder-faults: ignore unalign translation faults for prefetchesKorey Sewell
2009-05-12inorder-stc: update interface to handle store conditionalsKorey Sewell
2009-05-12inorder-float: Fix storage of FP resultsKorey Sewell
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from the actual floating point register file, the model can figure out what it needs to store
2009-05-12inorder-fetch: update model to use predecoderKorey Sewell
2009-05-12inorder-mem: clean up allocation/deletion of requests/packetsKorey Sewell
* * *
2009-05-12inorder-mem: skeleton support for prefetch/writehintsKorey Sewell
2009-05-12inorder-o3: allow both to compile togetherKorey Sewell
allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
2009-05-12inorder-unified-tlb: use unified TLB instead of old TLB modelKorey Sewell
2009-05-12inorder-miscregs: Fix indexing for misc. reg operands and update ↵Korey Sewell
result-types for better tracing of these types of values
2009-05-12inorder/alpha-isa: create eaComp object visible to StaticInst through ISAKorey Sewell
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * *
2009-05-12inorder-bpred: edits to handle non-delay-slot ISAsKorey Sewell
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
2009-05-12inorder-alpha-port: initial inorder support of ALPHAKorey Sewell
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.)
2009-05-05cpus: fix cpu progress eventKorey Sewell
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting progress events through repeatEvent flag and also changing the interval of the progress event as well
2009-04-21arm: Unify the ARM tlb. We forgot about this when we did the rest.Nathan Binkert
This code compiles, but there are no tests still
2009-04-20request: rename INST_READ to INST_FETCH.Steve Reinhardt
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19CPUs: Make the atomic CPU support locked memory accesses.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-04-19CPU: If the simple CPU is already idle, just return from suspendContext, ↵Gabe Black
don't assert.
2009-04-18o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ↵Korey Sewell
stage was not setting the predicted PC correctly or passing that information back to fetch correctly