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path: root/src/cpu
AgeCommit message (Expand)Author
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-06-29O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.Nathanael Premillieu
2012-06-08Timing CPU: Remove a redundant port pointerAndreas Hansson
2012-06-05cpu: Don't init simple and inorder CPUs if they are defered.Anthony Gutierrez
2012-06-05ISA: Back-out NoopMachInst as a StaticInstPtr change.Ali Saidi
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-06-04ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.Gabe Black
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-05-30Packet: Unify the use of PortID in packet and portAndreas Hansson
2012-05-26ISA,CPU: Generalize and split out the components of the decode cache.Gabe Black
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-05-25ISA: Make the decode function part of the ISA's decoder.Gabe Black
2012-05-25CPU: Simplify the implementation of the decode cache.Gabe Black
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-05-10gem5: fix some iterator use and erase bugsAli Saidi
2012-05-10gem5: fix a number of use after free issuesAli Saidi
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-25MEM: Add the PortId type and a corresponding id field to PortAndreas Hansson
2012-04-15CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.Gabe Black
2012-04-14Ruby: Use MasterPort base-class pointers where possibleAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
2012-04-06rubytest: remove spurious printfBrad Beckmann
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-05NetworkTest: remove unnecessary memory allocationTushar Krishna
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-30CPU: Unify initMemProxies across CPUs and simulation modesAndreas Hansson
2012-03-22Scons: Remove Werror=False in SConscript filesAndreas Hansson
2012-03-21O3: Fix sizing of decode to rename skid buffer.Andrew Lukefahr
2012-03-21O3: Fix size of skid buffer between fetch and decode when widths are differentBrian Grayson
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-19clang: Fix recently introduced clang compilation errorsAndreas Hansson
2012-03-11O3: Add fatal when fetchWidth > Impl::MaxWidth.Brian Grayson
2012-03-09O3/Ozone: Eliminate dead code counting software prefetch instsGeoffrey Blake
2012-03-09CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPUGeoffrey Blake
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-02DynInst: get rid of dead MyHash code.Steve Reinhardt
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-03-01x86: Fix switching of CPUsNilay Vaish
2012-02-24Ruby: Simplify tester ports by not using SimpleTimingPortAndreas Hansson
2012-02-24MEM: Move all read/write blob functions from Port to PortProxyAndreas Hansson
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson