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AgeCommit message (Expand)Author
2006-10-08Fixes for functional path.Ron Dreslinski
2006-10-08Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().Steve Reinhardt
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
2006-10-08Rename some vars for clarity.Steve Reinhardt
2006-10-06checkpoint recovery was screwed up because a new section was created in the m...Lisa Hsu
2006-10-06there are two main thrusts of this changeset.Lisa Hsu
2006-10-02Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-10-02Be sure to set progress interval.Kevin Lim
2006-10-02Updates to fix merge issues and bring almost everything up to working speed. ...Kevin Lim
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
2006-09-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-09-03Fix up the parameters to getInstRecordGabe Black
2006-09-03Fixing up parameters of getInstRecordGabe Black
2006-09-03A quick fix to isolate the tracing code to SPARCGabe Black
2006-08-31add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throug...Korey Sewell
2006-08-30Change the cpu pointer in the InstRecord object to a thread context pointer.Gabe Black
2006-08-29Extended the reg delta output.Gabe Black
2006-08-16Fixes for Kevins O3 model to work with the blocking caches.Ron Dreslinski
2006-08-15Some touchup to the reorganized includes and "using" directives.Gabe Black
2006-08-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
2006-08-15Fixed ALPHA_FS by moving the remnants of isa_fullsys_traits.hh into arch/alph...Gabe Black
2006-08-11Started to add support for O3 for sparc.Gabe Black
2006-08-11Started adding a system to output data after every instruction.Gabe Black
2006-08-11Pushed most of constants.hh back into isa_traits.hh and regfile.hh and create...Gabe Black
2006-07-26MIPS ISA runs 'hello world' in O3CPU ...Korey Sewell
2006-07-23Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...Korey Sewell
2006-07-21Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-21Minor functionality updates.Kevin Lim
2006-07-20Enforce the timing cpu ticking at it's clock rateAli Saidi
2006-07-19Minor changes to reflect state used for regression stats.Kevin Lim
2006-07-19Put regression tests back into m5. They are located in the "tests" directory...Kevin Lim
2006-07-19O3CPU fixes.Kevin Lim
2006-07-19Some minor compiling fixes.Kevin Lim
2006-07-14Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-14Fix the CheckerCPU being included via python.Kevin Lim
2006-07-14forgot tidKorey Sewell
2006-07-14For now, halt context is the same as deallocating.Korey Sewell
2006-07-13Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recen...Kevin Lim
2006-07-13Fix for bug when squashing and the fetching. Now fetch checks if the cache d...Kevin Lim
2006-07-13Update for changes to draining.Kevin Lim
2006-07-12memory mode information now contained in system objectAli Saidi
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-12Serialization changes to make O3CPU consistent with the other models.Kevin Lim
2006-07-12Updates for serialization. As long as the tickEvent doesn't need to be seria...Kevin Lim
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-12Track the PC of the cache data stored in fetch so it doesn't access memory mu...Kevin Lim
2006-07-11Fix ordering issue with squashed Icache Fetches and Static data in packet.Ron Dreslinski
2006-07-10Minor fixes.Kevin Lim
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