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path: root/src/cpu
AgeCommit message (Expand)Author
2012-12-11ruby: modify the directed tester to read/write streamsNilay Vaish
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
2012-12-06inorder cpu: add missing DPRINTF argumentMalek Musleh
2012-12-06o3 cpu: remove some unused buggy functions in the lsqNathanael Premillieu
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02cpu: O3 add a header declaring the DerivO3CPUAndreas Sandberg
2012-11-02cpu: Add header files for checker CPUsAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
2012-11-02o3: Fix a couple of issues with the local predictor.Mrinmoy Ghosh
2012-10-15memtest: move check on outstanding requestsNilay Vaish
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-09-25O3: Pack the comm structures a bit better to reduce their size.Ali Saidi
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-09-25CPU: Add abandoned instructions to O3 Pipe ViewerDjordje Kovacevic
2012-09-21TrafficGen: Add a basic traffic generatorAndreas Hansson
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-12Base CPU: Initialize profileEvent to NULLJoel Hestness
2012-09-12stats: remove duplicate instruction stats from the commit stageAnthony Gutierrez
2012-09-11Ruby: Use uint8_t instead of uint8 everywhereNilay Vaish
2012-09-07O3: Get rid of incorrect assert in RAS.Ali Saidi
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-28Port: Stricter port bind/unbind semanticsAndreas Hansson
2012-08-28Checker: Fix checker CPU portsAndreas Hansson
2012-08-27Ruby: Remove RubyEventQueueNilay Vaish
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-21CPU: Remove overloaded function_trace_start parameterAndreas Hansson
2012-08-21Clock: Make Tick unsigned and remove UTickAndreas Hansson
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-08-06process: add progName() virtual functionSteve Reinhardt
2012-07-27checker: make checker cpu id match its host's cpu idAnthony Gutierrez
2012-07-10ruby: remove the cpu assumptions for the random testerBrad Beckmann
2012-07-10cpu: added assertions to ensure the correct proxies are usedBrad Beckmann
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-06-29O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.Nathanael Premillieu
2012-06-08Timing CPU: Remove a redundant port pointerAndreas Hansson
2012-06-05cpu: Don't init simple and inorder CPUs if they are defered.Anthony Gutierrez
2012-06-05ISA: Back-out NoopMachInst as a StaticInstPtr change.Ali Saidi
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-06-04ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.Gabe Black
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson