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2006-10-23Fix fetch to stop fetching upon encountering a fault in SE mode. Also ↵Kevin Lim
change warning to a DPRINTF. --HG-- extra : convert_revision : 819bade049d7ffd97d316051c99146ece5e3a651
2006-10-23Add in support for LL/SC in the O3 CPU. Needs to be fully tested.Kevin Lim
src/cpu/base_dyn_inst.hh: Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code). src/cpu/base_dyn_inst_impl.hh: Add variable to track if the result of the instruction should be recorded. src/cpu/o3/alpha/cpu_impl.hh: Clear lock flag upon hwrei. src/cpu/o3/lsq_unit.hh: Use ISA specified handling of locked reads. src/cpu/o3/lsq_unit_impl.hh: Use ISA specified handling of locked writes. --HG-- extra : convert_revision : 1f5c789c35deb4b016573c02af4aab60d726c0e5
2006-10-18only do this assert after you know you're not switched out or idle.Lisa Hsu
--HG-- extra : convert_revision : 0cd0d31db44fe7e8e44bde90e1756873faca422f
2006-10-13Fix assertion. I haven't tested it fully (I can't reproduce Lisa's error) ↵Kevin Lim
but I believe it should fix what she's running into (which was definitely a bug). src/cpu/o3/fetch_impl.hh: Move assertion to area where it should really always be true. Sometimes you might recvRetry and not necessarily be blocked (if there was a squash). --HG-- extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018
2006-10-12Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem src/cpu/simple/timing.cc: hand merge --HG-- extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
2006-10-12Another memleak in the memtester (need [] with the delete)Ron Dreslinski
src/cpu/memtest/memtest.cc: Another memleak in the memtester --HG-- extra : convert_revision : f7ab079e90d578fb6b9d1ff238d049fcce55b01b
2006-10-12Fix a memory leak in the memtesterRon Dreslinski
--HG-- extra : convert_revision : 93062b0f1a3ba7a5210e2f27099f20ae8f66522b
2006-10-11some drain changes in timing (kevin's) and some memory mode assertion ↵Lisa Hsu
changes so that when you come out of resume, you only assert if you're really wrong. src/cpu/simple/atomic.cc: memory mode assertion change so that it only goes off if it's supposed to. src/cpu/simple/timing.cc: some drain changes (kevin's) and some changes to memoryMode assertions so that they don't go off when they're not supposed to. --HG-- extra : convert_revision : 007d8610f097e08f01367b905ada49f93cf37ca3
2006-10-11More cache fixes. Atomic coherence now works as well.Ron Dreslinski
src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Make Memtester able to test atomic as well src/mem/bus.cc: src/mem/bus.hh: Handle atomic snoops properly for cache->cache transfers src/mem/cache/cache_impl.hh: Debug output. Clean up memleak in atomic mode. Set hitLatency. Still need to send back reasonable number for atomic return value. src/mem/packet.cc: Add command strings for new commands src/python/m5/objects/MemTest.py: Add param to test atomic memory. --HG-- extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
2006-10-09Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/cpu/simple/timing.hh: tests/configs/o3-timing-mp.py: Hand merge. --HG-- extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
2006-10-09Comment out code that messed up SMT (but will be needed eventually).Kevin Lim
src/cpu/o3/cpu.cc: Comment out reseting CPU structures for now. This can be updated to work in the future. --HG-- extra : convert_revision : bc1a86e2fe47da5acb14ba8b64568b0355431f1c
2006-10-09Be sure to delete packet and sender state if the cache is blocked.Kevin Lim
src/cpu/o3/lsq_unit.hh: Be sure to delete data if the cache is blocked. --HG-- extra : convert_revision : fafbcfb8937e85555823942e69e798e557a600e5
2006-10-09Fix caches plus sampling switch over.Kevin Lim
src/cpu/o3/cpu.cc: Fix up caches plus sampling switch over. --HG-- extra : convert_revision : 49d0c16d4c5e8d5ba83749d568a4efe3b42e3a97
2006-10-09One step closet to having NACK's work.Ron Dreslinski
src/cpu/memtest/memtest.cc: Fix functional return path src/cpu/memtest/memtest.hh: Add snoop ranges in src/mem/cache/base_cache.cc: Properly signal NACKED src/mem/cache/cache_impl.hh: Catch nacked packet and panic for now --HG-- extra : convert_revision : 59a64e82254dfa206681c5f987e6939167754d67
2006-10-09Fix outstanding bug (FS#158).Kevin Lim
src/cpu/o3/cpu.cc: Extra debugging, fix a bug brought up on bug tracker. --HG-- extra : convert_revision : 23f8b166ba0d0af54e15b651ed28f59a1bc9d2f2
2006-10-09Fix checker bug.Kevin Lim
src/cpu/checker/thread_context.hh: Checker's TC should only copy state, and not fully take over from the old context (prevents it from accidentally stealing the quiesce event). --HG-- extra : convert_revision : 5760f9c5bae749f8d1df35e4c898df13e41b0224
2006-10-09Have cpus send snoop rangesRon Dreslinski
--HG-- extra : convert_revision : 2a1fba141e409ee1d7a0b69b5b21d236e3d4ce68
2006-10-09Put a check in so people know not to create more than 8 memtesters.Ron Dreslinski
--HG-- extra : convert_revision : 41ab297dc681b2601be1df33aba30c39f49466d8
2006-10-09Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : 77b06379a520dd91f124c0a543e30ec3a9cd1452
2006-10-09Update the Memtester, commit a config file/test for it.Ron Dreslinski
src/cpu/SConscript: Add memtester to the compilation environment. Someone who knows this better should make the MemTest a cpu model parameter. For now attached with the build of o3 cpu. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Update Memtest for new mem system src/python/m5/objects/MemTest.py: Update memtest python description --HG-- extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482
2006-10-08add in serialization of AtomicSimpleCPU _status. This is needed because ↵Lisa Hsu
right now unserializing breaks an assert since CPU status is not saved. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want. src/cpu/simple/atomic.cc: add in serialization of AtomicSimpleCPU _status. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want. --HG-- extra : convert_revision : 7000f660aecea6fef712bf81853d9a7b90d625ee
2006-10-08Fixes for functional path.Ron Dreslinski
If the cpu needs to update any state when it gets a functional write (LSQ??) then that code needs to be written. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: CPU's can recieve functional accesses, they need to determine if they need to do anything with them. src/mem/bus.cc: src/mem/bus.hh: Make the fuctional path do the correct tye of snoop --HG-- extra : convert_revision : 70d09f954b907a8aa9b8137579cd2b06e02ae2ff
2006-10-08Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().Steve Reinhardt
--HG-- extra : convert_revision : f22ce3221d270ecf8631d3dcaed05753accd5461
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation. src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. --HG-- extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
2006-10-08Rename some vars for clarity.Steve Reinhardt
--HG-- extra : convert_revision : 765283ae54d2d6b5885ea44c6c1813d4bcf18488
2006-10-08Record numCycles properly.Kevin Lim
src/cpu/simple/timing.cc: Record numCycles stat properly. src/cpu/simple/timing.hh: Extra variable to help record numCycles stat. --HG-- extra : convert_revision : 343311902831820264878aad41dc619999726b6b
2006-10-08Updates to O3 CPU. It should now work in FS mode, although sampling still ↵Kevin Lim
has a bug. src/cpu/o3/commit_impl.hh: Fixes for compile and sampling. src/cpu/o3/cpu.cc: Deallocate and activate threads properly. Also hopefully fix being able to use caches while switching over. src/cpu/o3/cpu.hh: Fixes for deallocating and activating threads. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit.hh: Handle getting back a BadAddress result from the access. src/cpu/o3/iew_impl.hh: More debug output. src/cpu/o3/lsq_unit_impl.hh: Fixup store conditional handling (still a bit of a hack, but works now). Also handle getting back a BadAddress result from the access. src/cpu/o3/thread_context_impl.hh: Deallocate context now records if the context should be fully removed. --HG-- extra : convert_revision : 55f81660602d0e25367ce1f5b0b9cfc62abe7bf9
2006-10-07Merge ktlim@zizzer:/bk/newmemKevin Lim
into zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/o3-merge/newmem --HG-- extra : convert_revision : b013b35f5c2264712eb51bef5623b208eb6128f9
2006-10-07Updates to bring MemTest closer to working with newmem. Ron still needs to ↵Kevin Lim
do the initial setup and configuration for it to work properly. src/SConscript: Include MemTest for now. It's not complete but it compiles so it shouldn't mess anything else up. --HG-- extra : convert_revision : 15a610c855b677fdced817850c92e4c911cf6d1c
2006-10-06checkpoint recovery was screwed up because a new section was created in the ↵Lisa Hsu
middle of another section and messed up unserializing. --HG-- extra : convert_revision : 7af15fdc9e8d203b26840a2eb5fef511b6a2b21d
2006-10-06there are two main thrusts of this changeset.Lisa Hsu
1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again). 2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier. src/arch/alpha/isa/decoder.isa: src/mem/cache/cache_impl.hh: modify arg. order for new calling convention of exitSimLoop. src/cpu/base.cc: src/sim/main.cc: src/sim/pseudo_inst.cc: src/sim/root.cc: now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args. src/sim/sim_events.cc: src/sim/sim_events.hh: src/sim/sim_exit.hh: add the periodicity of checkpointing back into the code. to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop). exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future. --HG-- extra : convert_revision : c61f4bf05517172edd2c83368fd10bb0f0678029
2006-10-02Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem --HG-- extra : convert_revision : 1010a4ee8e1abec0e8290637feee523ca9ef9a9b
2006-10-02Be sure to set progress interval.Kevin Lim
--HG-- extra : convert_revision : 793ca7d6af1deedf6b1fb4676288b11114f583a6
2006-10-02Updates to fix merge issues and bring almost everything up to working speed. ↵Kevin Lim
Ozone CPU remains untested, but everything else compiles and runs. src/arch/alpha/isa_traits.hh: This got changed to the wrong version by accident. src/cpu/base.cc: Fix up progress event to not schedule itself if the interval is set to 0. src/cpu/base.hh: Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here). src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: Remove float variable of instResult; it's always held within the double part now. src/cpu/checker/cpu_impl.hh: Use thread and not cpuXC. src/cpu/o3/alpha/cpu_builder.cc: src/cpu/o3/checker_builder.cc: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu_builder.cc: src/python/m5/objects/BaseCPU.py: Remove stats_reset_inst. src/cpu/o3/commit_impl.hh: src/cpu/ozone/lw_back_end_impl.hh: Get TC, not XCProxy. src/cpu/o3/cpu.cc: Switch out updates from the version of m5 I have. Also remove serialize code that got added twice. src/cpu/o3/iew_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/thread_state.hh: Remove code that was added twice. src/cpu/o3/lsq_unit.hh: Add back in stats that got lost in the merge. src/cpu/o3/lsq_unit_impl.hh: Use proper method to get flags. Also wake CPU if we're coming back from a cache miss. src/cpu/o3/thread_context_impl.hh: src/cpu/o3/thread_state.hh: Support profiling. src/cpu/ozone/cpu.hh: Update to use proper typename. src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/dyn_inst_impl.hh: Updates for newmem. src/cpu/ozone/lw_lsq_impl.hh: Get flags correctly. src/cpu/ozone/thread_state.hh: Reorder constructor initialization, use tc. src/sim/pseudo_inst.cc: Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext. --HG-- extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem configs/boot/micro_memlat.rcS: configs/boot/micro_tlblat.rcS: src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa_traits.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/params.hh: src/cpu/o3/checker_builder.cc: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/base.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.hh: src/dev/ide_disk.cc: src/python/m5/objects/O3CPU.py: src/python/m5/objects/Root.py: src/python/m5/objects/System.py: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/system.hh: util/m5/m5.c: Hand merge. --HG-- rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc rename : cpu/thread_state.hh => src/cpu/thread_state.hh rename : dev/ide_disk.hh => src/dev/ide_disk.hh rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py rename : python/m5/objects/System.py => src/python/m5/objects/System.py rename : sim/eventq.hh => src/sim/eventq.hh rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh rename : sim/serialize.cc => src/sim/serialize.cc rename : sim/stat_control.cc => src/sim/stat_control.cc rename : sim/stat_control.hh => src/sim/stat_control.hh rename : sim/system.hh => src/sim/system.hh extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
2006-09-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 91aacb435c223e8c37f6ba0a458b0dee55edcaf2
2006-09-03Fix up the parameters to getInstRecordGabe Black
--HG-- extra : convert_revision : 0fac43035a2510d3a3f596d3d8f57193045570f6
2006-09-03Fixing up parameters of getInstRecordGabe Black
--HG-- extra : convert_revision : 4ce06ac4f7d135cc04b39cf0e957a2539c7e946d
2006-09-03A quick fix to isolate the tracing code to SPARCGabe Black
--HG-- extra : convert_revision : 90c77f4d01101cad55f60d528b2a8be92d2f9aba
2006-08-31add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" ↵Korey Sewell
throughout CPU models src/arch/alpha/isa_traits.hh: src/arch/mips/isa_traits.hh: src/arch/sparc/isa_traits.hh: define 'ISA_HAS_DELAY_SLOT' src/cpu/base_dyn_inst.hh: src/cpu/o3/bpred_unit_impl.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rename_impl.hh: src/cpu/simple/base.cc: use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA --HG-- extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a
2006-08-30Change the cpu pointer in the InstRecord object to a thread context pointer.Gabe Black
--HG-- extra : convert_revision : 7efb2680cef4219281b94d680a4a7c75c123f89d
2006-08-29Extended the reg delta output.Gabe Black
--HG-- extra : convert_revision : 61c714a8c4faeb30d784b1ef1da0295474b8dc45
2006-08-16Fixes for Kevins O3 model to work with the blocking caches.Ron Dreslinski
src/cpu/o3/fetch_impl.hh: Fix ordering so dereference works src/cpu/o3/lsq_impl.hh: Check to make sure we didn't squash already src/cpu/o3/lsq_unit.hh: Fix for counting squashed retrys in the WB count src/cpu/o3/lsq_unit_impl.hh: Make sure to set retryID for stores, and clear it appropriately --HG-- extra : convert_revision : 689765a1baea7b36f13eb177d65e97b52b6da09f
2006-08-15Some touchup to the reorganized includes and "using" directives.Gabe Black
--HG-- extra : convert_revision : 956c80d6d826b08e52c0892a480a0a9b74b96b9d
2006-08-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem src/cpu/static_inst.hh: SCCS merged --HG-- extra : convert_revision : a4f6377dbd691ab58fe5f7958b983b092575f250
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
--HG-- extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
2006-08-15Fixed ALPHA_FS by moving the remnants of isa_fullsys_traits.hh into ↵Gabe Black
arch/alpha/pagetable.hh and fixing up some includes --HG-- extra : convert_revision : 02a47fa62b17245763314890beb68339c789d18f
2006-08-11Started to add support for O3 for sparc.Gabe Black
--HG-- extra : convert_revision : 3f94bda14024a09b9fbd7a5d13284d4987349ddf
2006-08-11Started adding a system to output data after every instruction.Gabe Black
src/arch/alpha/regfile.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/cpu/exetrace.hh: Added functions to start to support dumping register values once per cycle. src/cpu/exetrace.cc: Added some code to support printing the value of registers after each cycle. src/python/m5/main.py: Options to turn on output after every instruction. They are commented out. --HG-- extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0
2006-08-11Pushed most of constants.hh back into isa_traits.hh and regfile.hh and ↵Gabe Black
created a seperate file for the syscallreturn class. --HG-- extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 20:23:39 +0000