| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-05-12 | inorder-unified-tlb: use unified TLB instead of old TLB model | Korey Sewell | |
| 2009-05-12 | inorder-miscregs: Fix indexing for misc. reg operands and update ↵ | Korey Sewell | |
| result-types for better tracing of these types of values | |||
| 2009-05-12 | inorder/alpha-isa: create eaComp object visible to StaticInst through ISA | Korey Sewell | |
| Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * * | |||
| 2009-05-12 | inorder-bpred: edits to handle non-delay-slot ISAs | Korey Sewell | |
| Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline | |||
| 2009-05-12 | inorder-alpha-port: initial inorder support of ALPHA | Korey Sewell | |
| Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.) | |||
| 2009-05-05 | cpus: fix cpu progress event | Korey Sewell | |
| this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting progress events through repeatEvent flag and also changing the interval of the progress event as well | |||
| 2009-04-21 | arm: Unify the ARM tlb. We forgot about this when we did the rest. | Nathan Binkert | |
| This code compiles, but there are no tests still | |||
| 2009-04-20 | request: rename INST_READ to INST_FETCH. | Steve Reinhardt | |
| 2009-04-19 | Mem: Change isLlsc to isLLSC. | Gabe Black | |
| 2009-04-19 | CPUs: Make the atomic CPU support locked memory accesses. | Gabe Black | |
| 2009-04-19 | Memory: Rename LOCKED for load locked store conditional to LLSC. | Gabe Black | |
| 2009-04-19 | CPU: If the simple CPU is already idle, just return from suspendContext, ↵ | Gabe Black | |
| don't assert. | |||
| 2009-04-18 | o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ↵ | Korey Sewell | |
| stage was not setting the predicted PC correctly or passing that information back to fetch correctly | |||
| 2009-04-17 | o3, inorder: fix FS bug due to initializing ThreadState to Halted. | Steve Reinhardt | |
| For some reason o3 FS init() only called initCPU if the thread state was Suspended, which was no longer the case. There's no apparent reason to check, so I whacked the test completely rather than changing the check to Halted. The inorder init() was also updated to be symmetric, though the previous code was just a fancy no-op. | |||
| 2009-04-15 | o3: handle fetch with no active threads correctly. | Steve Reinhardt | |
| This situation can arise now on the first fetch cycle after the last active thread is halted. It seems easy enough to deal with when it happens rather than trying to avoid it. | |||
| 2009-04-15 | o3: fix {read,set}ArchFloatReg* functions. | Steve Reinhardt | |
| Register indices were not being calculated properly. | |||
| 2009-04-15 | ThreadState: initialize status to Halted in constructor. | Steve Reinhardt | |
| This provides a common initial status for all threads independent of CPU model (unlike the prior situation where CPUs initialized threads to inconsistent states). This mostly matters for SE mode; in FS mode, ISA-specific startupCPU() methods generally handle boot-time initialization of thread contexts (since the right thing to do is ISA-dependent). | |||
| 2009-04-15 | Get rid of the Unallocated thread context state. | Steve Reinhardt | |
| Basically merge it in with Halted. Also had to get rid of a few other functions that called ThreadContext::deallocate(), including: - InOrderCPU's setThreadRescheduleCondition. - ThreadContext::exit(). This function was there to avoid terminating simulation when one thread out of a multi-thread workload exits, but we need to find a better (non-cpu-centric) way. | |||
| 2009-04-08 | tlb: More fixing of unified TLB | Nathan Binkert | |
| 2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black | |
| 2009-03-11 | cpu: fix minor endian issue with trace output | Steve Reinhardt | |
| (no functional change) | |||
| 2009-03-07 | stats: fix duplicate statistics names. | Nathan Binkert | |
| This generally requires providing a more meaningful name() function for a class. | |||
| 2009-03-05 | stats: Fix all stats usages to deal with template fixes | Nathan Binkert | |
| 2009-03-05 | Get rid of 'using namespace' declarations in headers. | Steve Reinhardt | |
| 2009-03-04 | InOrderCPU: Clean up Constructors to initialize variables correctly (i.e. in ↵ | Korey Sewell | |
| a way for the compiler to play *nice*) | |||
| 2009-03-04 | Give each resource in InOrder it's own TraceFlag instead of just standard ↵ | Korey Sewell | |
| 'Resource' flag | |||
| 2009-03-04 | Remove unused functions/comments cluttering up the code. | Korey Sewell | |
| 2009-03-04 | make handling of interstage buffers (i.e. StageQueues) more consistent: ↵ | Korey Sewell | |
| (1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads | |||
| 2009-03-04 | InOrder didnt have all it's params set to a default value, which is now ↵ | Korey Sewell | |
| required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before we assume they are OK for use. | |||
| 2009-03-04 | Give TimeBuffer an ID that can be set. Necessary because InOrder uses ↵ | Korey Sewell | |
| generic stages so w/o an ID there is no way to differentiate buffers when debugging | |||
| 2009-03-04 | use numCycles instead of simTicks to determine CPI stat in InOrder | Korey Sewell | |
| 2009-03-04 | O3: Make numThreads error message more helpful. | Steve Reinhardt | |
| 2009-02-27 | Processes: Make getting and setting system call arguments part of a process ↵ | Gabe Black | |
| object. | |||
| 2009-02-26 | CPA: Add code to automatically record function symbols as CPU executes. | Ali Saidi | |
| 2009-02-25 | CPU: Only look up the nearest symbol in the kernel if you're actually in ↵ | Gabe Black | |
| kernel code. | |||
| 2009-02-25 | CPU: Add a flag to identify a read barrier to the static inst class. | Gabe Black | |
| 2009-02-25 | CPU: Don't fetch when executing a macroop. | Gabe Black | |
| If the CPL changes mid macroop, the end of the instruction might not be priveleged enough to execute the beginning. | |||
| 2009-02-25 | CPU: Implement translateTiming which defers to translateAtomic, and convert ↵ | Gabe Black | |
| the timing simple CPU to use it. | |||
| 2009-02-25 | ISA: Replace the translate functions in the TLBs with translateAtomic. | Gabe Black | |
| 2009-02-25 | CPU: Get rid of translate... functions from various interface classes. | Gabe Black | |
| 2009-02-23 | debug: Move debug_break into src/base | Nathan Binkert | |
| 2009-02-20 | Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up ↵ | Korey Sewell | |
| comments and O3 extensions InOrder Thread Context | |||
| 2009-02-16 | Fixes to get prefetching working again. | Steve Reinhardt | |
| Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too. | |||
| 2009-02-10 | style | Nathan Binkert | |
| 2009-02-10 | Configs: Add support for the InOrder CPU model | Korey Sewell | |
| 2009-02-10 | InOrder: Import new inorder CPU model from MIPS. | Korey Sewell | |
| This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen! | |||
| 2009-02-10 | ExeTrace: Allow subclasses of the tracer to define their own prefix to dump | Korey Sewell | |
| 2009-02-10 | CPU: Prepare CPU models for the new in-order CPU model. | Korey Sewell | |
| Some new functions and forward declarations are necessary to make things work | |||
| 2009-02-01 | CPU: Don't always reset the micro pc on faults. Let the faults handle it. | Gabe Black | |
| 2009-02-01 | X86: Make sure the predecoder is cleared out for interrupts. | Gabe Black | |
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