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AgeCommit message (Expand)Author
2018-11-22cpu: Made LTAGE parameters configurablePau Cabre
2018-11-22cpu: Fixed useful counter handling in LTAGEPau Cabre
2018-11-22cpu: Fixes on the loop predictor part of LTAGEPau Cabre
2018-11-17cpu: Fix LTAGE max number of allocations on updatePau Cabre
2018-11-17configs: Added an option for choosing branch predictor typePau Cabre
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
2018-11-14cpu: Fixed ratio of pred to hyst bits for LTAGE BimodalPau Cabre
2018-11-13cpu: Fixed PC shifting on LTAGE branch predictorPau Cabre
2018-10-09cpu: Fix MinorCPU executing Crypto InstructionsGiacomo Travaglini
2018-10-09arch-arm: AArch32 Crypto AESMatt Horsnell
2018-10-09arch-arm: AArch32 Crypto SHAMatt Horsnell
2018-10-01cpu: Fix typo in header guard for Noncaching cpuGiacomo Travaglini
2018-09-13Fix SConstruct for asan buildEarl Ou
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
2018-08-24cpu: Stream/SubstreamID support in TrafficGenGiacomo Travaglini
2018-08-24cpu: Turn BaseTrafficGen numSuppressed into a statMichiel W. van Tol
2018-08-21misc: Appease GCC 8Jason Lowe-Power
2018-08-17scons,ruby: do not generate unnecessary filesBrandon Potter
2018-08-10cpu: Add hash functionality for RegId classBradley Wang
2018-08-10cpu: Removed unnecessary file reg_class_impl.hhBradley Wang
2018-07-25cpu: Warn when (un)serializing a traffic generatorGiacomo Travaglini
2018-07-25cpu: Allow creation of traffic gen from generic SimObjectsGiacomo Travaglini
2018-07-24cpu-o3: Missing freeing the heads of DepGraph in IQ squashingHanhwi Jang
2018-07-13cpu: Add a Python-enabled traffic generatorAndreas Sandberg
2018-07-13cpu: Support trace termination in BaseTrafficGenAndreas Sandberg
2018-07-13cpu: Unify error handling for address generatorsAndreas Sandberg
2018-07-13cpu: Split the traffic generator into two classesAndreas Sandberg
2018-06-28cpu: Remove reduntant protobuf includesAndreas Sandberg
2018-06-21cpu: Fix bug introduced by RequestPtr type changeGiacomo Travaglini
2018-06-14cpu: Prevent suspended TimingSimple CPUs from fetching next instructionsTuan Ta
2018-06-14cpu: add a new instruction type 'Atomic'Tuan Ta
2018-06-14cpu-minor: Remove redundant thread startup callAndreas Sandberg
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-05-29cpu: Avoid unnecessary dynamic_pointer_cast in atomic modelGiacomo Travaglini
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
2018-03-27cpu: Remove ExtMachInst typedefs from the O3 CPU model.Gabe Black
2018-03-27arch: cpu: Make the ExtMachInst type a template argument in InstMap.Gabe Black
2018-03-27cpu: Stop extracting inst_flags from the machInst.Gabe Black
2018-03-26cpu: Use the new asBytes function in the protobuf inst tracer.Gabe Black
2018-03-26arch: Add a virtual asBytes function to the StaticInst class.Gabe Black
2018-03-23ruby: Make sure addresses print in hexJason Lowe-Power
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
2018-02-20cpu-o3: Don't add non-speculative mem barriers to the IQ twiceAndreas Sandberg
2018-02-05cpu: MinorCPU handling IsSquashAfter flagGiacomo Travaglini
2018-01-29arm: DT autogeneration - Generate cpus nodeGlenn Bergmans
2018-01-12sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().Xiaoyu Ma
2018-01-11cpu: Make the CPU's TLB parameter a BaseTLB.Gabe Black
2018-01-10style: change C/C++ source permissions to noexecBKP
2018-01-10alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.Gabe Black
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