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path: root/src/cpu
AgeCommit message (Expand)Author
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-13BPred: Fix RAS to handle predicated call/return instructions.Mrinmoy Ghosh
2012-02-13BP: Fix several Branch Predictor issues.Mrinmoy Ghosh
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12cpu: add separate stats for insts/ops both globally and per cpu modelAnthony Gutierrez
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-10O3 CPU: Improve handling of delayed commit flagNilay Vaish
2012-02-10O3 CPU: Strengthen condition for handling interruptsNilay Vaish
2012-02-10O3 CPU: Provide the squashing instructionNilay Vaish
2012-02-10O3 Fetch: Check if PC is pointing to Microcode ROMNilay Vaish
2012-02-10SE/FS: Record the system pointer all the time for the simple CPU.Gabe Black
2012-02-07Checker: Access workload element 0 only if there is an element 0.Gabe Black
2012-02-07Faults: Turn off arch/faults.hhGabe Black
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-31Thread: Use inherited baseCpu rather than cpu in SimpleThreadAndreas Hansson
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-30Merge with main repository.Gabe Black
2012-01-30MEM: Clean-up of Functional/Virtual/TranslatingPort remnantsAndreas Hansson
2012-01-29Yet another merge with the main repository.Gabe Black
2012-01-29Implement Ali's review feedback.Gabe Black
2012-01-28O3 CPU LSQ: Implement TSONilay Vaish
2012-01-28Merge with the main repo.Gabe Black
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
2012-01-17CPU: Moving towards a more general port across CPU modelsAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-12inorder: MDU deadlock fixMaximilien Breughe
2012-01-10DPRINTF: Improve some dprintf messages.Nilay Vaish
2012-01-09CPU: Remove Alpha-specific PC alignment check.Anders Handler
2012-01-09O3: Remove some asserts that no longer seem to be valid.Ali Saidi
2012-01-09O3: Add support of function tracing with O3 CPU.Ali Saidi
2012-01-09MAC: Make gem5 compile and run on MacOSX 10.7.2Andreas Hansson
2012-01-07Another merge with the main repository.Gabe Black
2012-01-07Merge with the main repository again.Gabe Black
2012-01-07Merge with main repository.Gabe Black
2011-12-13gcc: fix unused variable warnings from GCC 4.6.1Nathan Binkert
2011-12-01Output: Add hierarchical output support and cleanup existing codebase.Chris Emmons
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
2011-12-01ARM: Add support for having a TLB cache.Ali Saidi
2011-12-01O3: Add stat that counts how many cycles the O3 cpu was quiesced.Ali Saidi
2011-11-18SE/FS: Get rid of includes of config/full_system.hh.Gabe Black
2011-11-18SE/FS: Get rid of FULL_SYSTEM in the CPU directory.Gabe Black
2011-11-03Ruby: Remove some unused typedefsNilay Vaish
2011-11-02SE/FS: Get rid of FULL_SYSTEM in sim.Gabe Black
2011-11-01SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.Gabe Black
2011-11-01SE/FS: Expose the same methods on the CPUs in SE and FS modes.Gabe Black