gem5 - gem5

Age	Commit message (Expand)	Author
2013-10-31	cpu: Construct ROB with cpu params struct instead of each variable	Faissal Sleiman
2013-10-31	cpu: Fix O3 issuse with load+barrier instructions.	Ali Saidi
2013-10-17	cpu: add consistent guarding to *_impl.hh files.	Matt Horsnell
2013-10-17	cpu: Removing an unused variable in rename	Faissal Sleiman
2013-10-17	cpu: Change IEW DPRINTF to use IEW debug flag	Faissal Sleiman
2013-10-17	cpu: Put in assertions to check for maximum supported LQ/SQ size	Faissal Sleiman
2013-10-17	cpu: Fix O3 uncacheable load that is replayed but misses the TLB	Ali Saidi
2013-10-16	kvm: Fix latency calculation of IPR accesses	Andreas Sandberg
2013-10-15	arch/x86: add support for explicit CC register file	Yasuko Eckert
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu/o3: clean up rename map and free list	Steve Reinhardt
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
2013-10-15	cpu/o3: clean up scoreboard object	Steve Reinhardt
2013-10-15	cpu/o3: clean up physical register file	Steve Reinhardt
2013-10-15	cpu/inorder: merge register class enums	Steve Reinhardt
2013-10-15	cpu: clean up architectural register classification	Steve Reinhardt
2013-10-03	kvm: Service events in the instruction event queues	Andreas Sandberg
2013-09-30	kvm: Add support for thread-specific instruction events	Andreas Sandberg
2013-09-30	kvm: FPU synchronization support on x86	Andreas Sandberg
2013-09-30	kvm: x86: Fix segment registers to make them VMX compatible	Andreas Sandberg
2013-09-25	kvm: Add x86 segment register verification to help debugging	Andreas Sandberg
2013-09-25	kvm: Initial x86 support	Andreas Sandberg
2013-09-19	kvm: Correctly handle the return value from handleIpr(Read\|Write)	Andreas Sandberg
2013-09-19	kvm: Fix a case where the run timers weren't armed properly	Andreas Sandberg
2013-09-11	cpu: Dynamically instantiate O3 CPU LSQUnits	Joel Hestness
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson
2013-09-04	cpu: Move the branch predictor out of the BaseCPU	Andreas Hansson
2013-09-04	arch: Header clean up for NOISA resurrection	Andreas Hansson
2013-08-20	cpu: Fix timing CPU isDrained comment formatting	Andreas Hansson
2013-08-19	cpu: Accurately count idle cycles for simple cpu	Lena Olson
2013-08-19	cpu: Fix TrafficGen trace playback	Sascha Bischoff
2013-08-19	cpu: Fix timing CPU drain check	Andreas Hansson
2013-08-19	cpu: Fix a bug in the O3 CPU introduced by the cache line patch	Andreas Hansson
2013-07-19	cpu: Remove unused getBranchPred() method from BaseCPU	Andreas Sandberg
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-07-15	debug : Fixes the issue wherein Debug symbols were not getting dumped into tr...	Umesh Bhaskar
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Remove redundant explicit setting of default clocks	Akash Bagdia
2013-06-27	cpu: Consider instructions waiting for FU completion in draining	Andreas Hansson
2013-06-18	kvm: Use the address finalization code in the TLB	Andreas Sandberg
2013-06-11	kvm: Add more VM stats	Andreas Sandberg
2013-06-11	kvm: Separate host frequency from simulated CPU frequency	Andreas Sandberg
2013-06-11	kvm: Don't handle IO and execute in the same tick	Andreas Sandberg
2013-06-11	kvm: Maintain a local instruction counter and update totalNumInsts	Andreas Sandberg
2013-06-11	cpu: Add support for scheduling multiple inst/load stop events	Andreas Sandberg
2013-06-03	kvm: Allow architectures to override the cycle accounting mechanism	Andreas Sandberg
2013-06-03	kvm: Add handling of EAGAIN when creating timers	Andreas Sandberg
2013-06-03	kvm: Add a call to thread->startup() in startup()	Andreas Sandberg
2013-05-30	cpu: Prune the stale TraceCPU	Andreas Hansson
2013-05-30	cpu: Check that minimum TrafficGen period is less than max period	Sascha Bischoff