index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
cpu
Age
Commit message (
Expand
)
Author
2010-06-02
ARM: Implement ARM CPU interrupts
Ali Saidi
2010-06-02
ARM: Move PC mode bits around so they can be used for exectrace
Ali Saidi
2010-06-02
Simple CPU: Make the FloatRegs trace flag do something.
Gabe Black
2010-06-02
CPU: Reset fetch offset after a exception
Ali Saidi
2010-06-02
ARM: Make the predecoder handle Thumb instructions.
Gabe Black
2010-05-13
BPRED: Fixed the treshold-bug in the tournament predictor.
Maximilien Breughe
2010-04-15
tick: rename Clock namespace to SimClock
Nathan Binkert
2010-04-10
inorder: timing for inst forwarding
Korey Sewell
2010-04-02
ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base
Nathan Binkert
2010-04-02
ruby: get "using namespace" out of headers
Nathan Binkert
2010-03-29
style: cleanup the Ruby Tester
Nathan Binkert
2010-03-27
m5: merge inorder updates
Korey Sewell
2010-03-27
inorder: write-hints bug fix
Korey Sewell
2010-03-25
CPU: Added comments to address translation classes.
Timothy M. Jones
2010-03-23
cpu: get rid of uncached access "events"
Steve Reinhardt
2010-03-23
cpu: fix exec tracing memory corruption bug
Steve Reinhardt
2010-03-22
inorder: import name for addtl. bpred stats
Korey Sewell
2010-03-22
inorder: fix squash bug in branch predictor
Maximilien Breughe
2010-03-22
inorder: fix address list bug
Korey Sewell
2010-03-21
TimingSimpleCPU: Fixed uncacacheable request read bug
Brad Beckmann
2010-03-10
ruby: get rid of std-includes.hh
Nathan Binkert
2010-02-26
cpu_models: get rid of cpu_models.py and move the stuff into SCons
Nathan Binkert
2010-02-20
BaseDynInst: Preserve the faults returned from read and write.
Timothy M. Jones
2010-02-12
O3PCU: Split loads and stores that cross cache line boundaries.
Timothy M. Jones
2010-02-12
BaseDynInst: Make the TLB translation timing instead of atomic.
Timothy M. Jones
2010-01-31
inorder: double delete inst bug
Korey Sewell
2010-01-31
inorder: inst count mgmt
Korey Sewell
2010-01-31
inorder: implement split stores
Korey Sewell
2010-01-31
inorder: implement split loads
Korey Sewell
2010-01-31
inorder: add activity stats
Korey Sewell
2010-01-31
inorder: object cleanup in destructors
Korey Sewell
2010-01-31
inorder: user per-thread dummy insts/reqs
Korey Sewell
2010-01-31
inorder: add execution unit stats
Korey Sewell
2010-01-31
inorder: recvRetry bug fix
Korey Sewell
2010-01-31
inorder-stats: add prereq to basic stat
Korey Sewell
2010-01-31
inorder: ctxt switch stats
Korey Sewell
2010-01-31
inorder: pipeline stage stats
Korey Sewell
2010-01-31
inorder: enforce stage bandwidth
Korey Sewell
2010-01-31
inorder: set thread status'
Korey Sewell
2010-01-31
inorder: add/remove halt/deallocate context respectively
Korey Sewell
2010-01-31
inorder: track last branch committed
Korey Sewell
2010-01-31
inorder: add updatePC event to resPool
Korey Sewell
2010-01-31
inorder: ready thread wakeup
Korey Sewell
2010-01-31
inorder: add threadmodel flag
Korey Sewell
2010-01-31
inorder: mem. mgmt. update
Korey Sewell
2010-01-31
inorder: suspend in respool
Korey Sewell
2010-01-31
inorder: fetch thread bug
Korey Sewell
2010-01-31
inorder: ready/suspend status fns
Korey Sewell
2010-01-31
inorder-cleanup: remove unused thread functions
Korey Sewell
2010-01-31
inorder: activate thread on cache miss
Korey Sewell
[next]