gem5 - gem5

Age	Commit message (Expand)	Author
2014-05-09	arch, arm: Preserve TLB bootUncacheability when switching CPUs	Geoffrey Blake
2014-05-09	cpu: add more instruction mix statistics	Curtis Dunham
2014-05-09	cpu, arm: Allow the specification of a socket field	Akash Bagdia
2014-04-23	cpu: Fix setTranslateLatency() bug for squashed instructions	Mitchell Hayenga
2014-04-01	cpu: Fix case where o3 lsq could print out uninitialized data	Mitch Hayenga
2014-04-23	cpu: Add O3 CPU width checks	Dam Sunwoo
2014-04-19	o3: Fix occupancy checks for SMT	Faissal Sleiman
2014-04-09	kvm, x86: Add initial support for multicore simulation	Andreas Sandberg
2014-03-25	cpu: o3: lsq: Fix TSO implementation	Marco Elver
2014-03-23	cpu: DRAM Traffic Generator	Neha Agarwal
2014-03-23	cpu: Add basic check to TrafficGen initial state	Stan Czerniawski
2014-03-16	kvm: Clean up signal handling	Andreas Sandberg
2014-03-16	kvm: x86: Adjust PC to remove the CS segment base address	Andreas Sandberg
2014-03-16	kvm: x86: Add support for x86 INIT and STARTUP handling	Andreas Sandberg
2014-03-12	alpha: Small removal of dead comments/code from alpha ISA	Paul Rosenfeld
2014-03-07	cpu: Make CPU and ThreadContext getters const	Andreas Hansson
2014-03-07	scons: Fixes uninitialized warnings issued by clang	Mitch Hayenga
2014-03-03	kvm: x86: Always assume segments to be usable	Andreas Sandberg
2014-03-03	kvm: Initialize signal handlers from startupThread()	Andreas Sandberg
2014-03-01	cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPU	Christopher Torng
2014-02-20	kvm: Add support for multi-system simulation	Andreas Sandberg
2014-02-09	cpu: simple: Add support for using branch predictors	Andreas Sandberg
2014-01-29	cpu: fix bug when TrafficGen deschedules event	Xiangyu Dong
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2014-01-24	checker: CheckerCPU handling of MiscRegs was incorrect	Geoffrey Blake
2014-01-24	arch, cpu: Add support for flattening misc register indexes.	Ali Saidi
2014-01-24	cpu: Add support for Memory+Barrier instruction types in O3 cpu.	Giacomo Gabrielli
2014-01-24	cpu: Add support for instructions that zero cache lines.	Ali Saidi
2014-01-24	cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...	Ali Saidi
2014-01-24	mem: per-thread cache occupancy and per-block ages	Dam Sunwoo
2014-01-24	base: add support for probe points and common probes	Matt Horsnell
2014-01-24	mem: track per-request latencies and access depths in the cache hierarchy	Matt Horsnell
2014-01-24	cpu: Relax check on squashed non-speculative instructions	Andreas Hansson
2014-01-24	cpu: remove faulty simpoint basic block inst count assertion	Dam Sunwoo
2013-12-03	cpu: call BaseCPU startup() function in o3 cpu	Nilay Vaish
2013-10-15	kvm: Set the perf exclude_host attribute if available	Andreas Sandberg
2013-11-26	kvm: Remove the unused hostFreq member from BaseKvmCPU	Andreas Sandberg
2013-11-25	sim: simulate with multiple threads and event queues	Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-15	cpu: allow the fetch buffer to be smaller than a cache line	Anthony Gutierrez
2013-11-15	cpu: Fix Checker register index use	Andreas Hansson
2013-10-31	cpu: Construct ROB with cpu params struct instead of each variable	Faissal Sleiman
2013-10-31	cpu: Fix O3 issuse with load+barrier instructions.	Ali Saidi
2013-10-17	cpu: add consistent guarding to *_impl.hh files.	Matt Horsnell
2013-10-17	cpu: Removing an unused variable in rename	Faissal Sleiman
2013-10-17	cpu: Change IEW DPRINTF to use IEW debug flag	Faissal Sleiman
2013-10-17	cpu: Put in assertions to check for maximum supported LQ/SQ size	Faissal Sleiman
2013-10-17	cpu: Fix O3 uncacheable load that is replayed but misses the TLB	Ali Saidi
2013-10-16	kvm: Fix latency calculation of IPR accesses	Andreas Sandberg
2013-10-15	arch/x86: add support for explicit CC register file	Yasuko Eckert
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert