Age | Commit message (Collapse) | Author |
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--HG--
extra : convert_revision : 09610ad84afa605db2d0eab9945eb9809f297182
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People should never put pointers in DPRINTFs; it messes up
tracediffs. Plus these used the FullCPU trace flag, which
is not right.
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extra : convert_revision : 82ed56757da0ad947c165ba205b5f752c85c6667
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The correct order is unintuitively rax, rcx, rdx, rbx, etc, not rax, rbx, rcx, rdx.
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These need to be refined a little still and given parameters.
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extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
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Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg.
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extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
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creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
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--HG--
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src/arch/mips/SConscript:
"mips import pt.1".
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro
src/cpu/o3/fetch_impl.hh:
hand merge
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extra : convert_revision : 2b10076a24cb36cb748e299011ae691f09c158cd
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Caused slowdown in performance instead of speeding up.
src/cpu/base.cc:
Removed "adding instead of dividing" trick.
src/mem/bus.cc:
Fixed spelling in comments.
Removed "adding instead of dividing" trick.
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--HG--
extra : convert_revision : 1c920b050c21e592a386410e4e9f45354f8e4441
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supposed to and make sure parameters have the right type.
Also make sure that any object that should be an intermediate
type has the right options set.
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extra : convert_revision : d56910628d9a067699827adbc0a26ab629d11e93
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into doughnut.hpl.hp.com:/home/gblack/newmem-o3-micro
src/cpu/base_dyn_inst_impl.hh:
src/cpu/o3/fetch_impl.hh:
Hand merge
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extra : convert_revision : 0c0692033ac30133672d8dfe1f1a27e9d9e95a3d
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--HG--
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is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.
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extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
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the time it was repsonded to. In timing mode the
time it was responded to is curTick. Doesn't change the results, but it does make implementation of nextCycle() more difficult
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extra : convert_revision : 67ed6261a5451d17d96d5df45992590acc353afc
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No need to initialize memory contents; should come up as 0.
src/cpu/memtest/memtest.cc:
No need to initialize memory contents; should come up as 0.
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extra : convert_revision : 1713676956f3d33b4686fee2650bd17027bcc495
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Make code compatible with new decode method.
src/arch/alpha/remote_gdb.cc:
src/cpu/base_dyn_inst_impl.hh:
src/cpu/exetrace.cc:
src/cpu/simple/base.cc:
Make code compatible with new decode method.
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
Modified instruction decode method.
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extra : convert_revision : a9a6d3a16fff59bc95d0606ea344bd57e71b8d0a
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--HG--
extra : convert_revision : 8af0dd9c16e7db8ed92f7a71c396841d5ae7e072
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"moreBytes" which just takes a MachInst.
src/arch/x86/predecoder.cc:
Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes.
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extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : 1d2efac895a1c8328026a079e0b319a436325616
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src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
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extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f
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real thing. Also rename the null case to something that can
be a C++ symbol.
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--HG--
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--HG--
extra : convert_revision : 8ee88bff8010dcb7a412f6a6b49d40fad1c0bb68
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bit in the ExtMachInst.
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--HG--
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--HG--
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
src/cpu/simple/base.cc:
Hand merge
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extra : convert_revision : a2902ef9d917d22ffb9c7dfa2fd444694a65240d
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into zamp.eecs.umich.edu:/.automount/greenville/w/acolyte/newmem
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extra : convert_revision : c80b7ef5a2cc4ab1b86bb1eef7fae91886a7737d
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Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls.
exec tracing isn't needed for m5.fast binaries
Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead.
src/arch/sparc/miscregfile.cc:
Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead.
src/cpu/simple/base.cc:
Assign traceData to be NULL at BaseSimpleCPU constructor.
Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls.
exec tracing isn't needed for m5.fast binaries
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--HG--
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--HG--
extra : convert_revision : bccafe884e58a55b02ff408448e6644196e439a4
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the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
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into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86
--HG--
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--HG--
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and schedules the event immediately.
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extra : convert_revision : a84e729a5ef3632cbe6cff858c453c782707d983
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into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86
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extra : convert_revision : 3f17fc418ee5a30da2b08a515fb394cc8fcdd237
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--HG--
extra : convert_revision : cf68886d53301e0a63705247bd7d66b2ff08ea84
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-all- arguements are truncated to 32 bits, but we should be able to get away with it.
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extra : convert_revision : 3b8766c68a4ab36e2e769fac4812657f3f7e0d1c
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into doughnut.mwconnections.com:/home/gblack/newmem-o3-micro
--HG--
extra : convert_revision : 56c2205cdbb9af64c30b381a80b4d14c97841da7
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into doughnut.mwconnections.com:/home/gblack/newmem-o3-micro
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extra : convert_revision : 545b9e98eb1895f4b9e782224fb6615c71ed6323
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--HG--
extra : convert_revision : 56f6f2cbf4e92b7f2dd8c9453831fab86d83ef80
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it always returns true and nacks the packet if there isn't sufficient buffer space
fix the timing cpu to handle receiving a nacked packet
src/cpu/simple/timing.cc:
make the timing cpu handle receiving a nacked packet
src/mem/bridge.cc:
src/mem/bridge.hh:
the bridge never returns false when recvTiming() is called on its ports now, it always returns true and nacks the packet if there isn't sufficient buffer space
--HG--
extra : convert_revision : 5e12d0cf6ce985a5f72bcb7ce26c83a76c34c50a
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--HG--
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--HG--
extra : convert_revision : 8cc2943ebc41e4d430789ee7923dd0dc878be06b
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head
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extra : convert_revision : 11df5fb2a8f1fa020d042e75b22a7f2f2bcbd9ab
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro
--HG--
extra : convert_revision : 757e1d79033e6f8e0aaaf5ecaf14077d416cff8e
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