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cpu
Age
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Author
2013-01-07
cpu: Remove unused params.hh header file in inorder CPU
Andreas Sandberg
2013-01-07
cpu: Introduce sanity checks when switching between CPUs
Andreas Sandberg
2013-01-07
cpu: Correctly call parent on switchOut() and takeOverFrom()
Andreas Sandberg
2013-01-07
cpu: Unify SimpleCPU and O3 CPU serialization code
Andreas Sandberg
2013-01-07
cpu: Initialize the O3 pipeline from startup()
Andreas Sandberg
2013-01-07
cpu: Implement a flat register interface in thread contexts
Andreas Sandberg
2013-01-07
arch: Move the ISA object to a separate section
Andreas Sandberg
2013-01-07
cpu: Check that the memory system is in the correct mode
Andreas Sandberg
2013-01-07
cpu: Share the send functionality between traffic generators
Andreas Hansson
2013-01-07
cpu: Add support for protobuf input for the trace generator
Andreas Hansson
2013-01-07
cpu: Encapsulate traffic generator input in a stream
Andreas Hansson
2013-01-07
cpu: Fix the traffic gen read percentage
Andreas Hansson
2013-01-07
arch: Make the ISA class inherit from SimObject
Andreas Sandberg
2013-01-07
o3: Fix issue with LLSC ordering and speculation
Ali Saidi
2013-01-07
cpu: rename the misleading inSyscall to noSquashFromTC
Ali Saidi
2013-01-04
Decoder: Remove the thread context get/set from the decoder.
Gabe Black
2012-12-11
ruby: modify the directed tester to read/write streams
Nilay Vaish
2012-12-06
TournamentBP: Fix some bugs with table sizes and counters
Erik Tomusk
2012-12-06
inorder cpu: add missing DPRINTF argument
Malek Musleh
2012-12-06
o3 cpu: remove some unused buggy functions in the lsq
Nathanael Premillieu
2012-11-02
sim: Move the draining interface into a separate base class
Andreas Sandberg
2012-11-02
cpu: O3 add a header declaring the DerivO3CPU
Andreas Sandberg
2012-11-02
cpu: Add header files for checker CPUs
Andreas Sandberg
2012-11-02
sim: Include object header files in SWIG interfaces
Andreas Sandberg
2012-11-02
ARM: dump stats and process info on context switches
Dam Sunwoo
2012-11-02
o3: Fix a couple of issues with the local predictor.
Mrinmoy Ghosh
2012-10-15
memtest: move check on outstanding requests
Nilay Vaish
2012-10-15
Port: Add protocol-agnostic ports in the port hierarchy
Andreas Hansson
2012-10-15
Fix: Address a few minor issues identified by cppcheck
Andreas Hansson
2012-10-15
Regression: Use CPU clock and 32-byte width for L1-L2 bus
Andreas Hansson
2012-09-25
O3: Pack the comm structures a bit better to reduce their size.
Ali Saidi
2012-09-25
ARM: Squash outstanding walks when instructions are squashed.
Ali Saidi
2012-09-25
sim: Move CPU-specific methods from SimObject to the BaseCPU class
Andreas Sandberg
2012-09-25
CPU: Add abandoned instructions to O3 Pipe Viewer
Djordje Kovacevic
2012-09-21
TrafficGen: Add a basic traffic generator
Andreas Hansson
2012-09-19
AddrRange: Transition from Range<T> to AddrRange
Andreas Hansson
2012-09-12
Base CPU: Initialize profileEvent to NULL
Joel Hestness
2012-09-12
stats: remove duplicate instruction stats from the commit stage
Anthony Gutierrez
2012-09-11
Ruby: Use uint8_t instead of uint8 everywhere
Nilay Vaish
2012-09-07
O3: Get rid of incorrect assert in RAS.
Ali Saidi
2012-09-07
Param: Transition to Cycles for relevant parameters
Andreas Hansson
2012-08-28
Clock: Add a Cycles wrapper class and use where applicable
Andreas Hansson
2012-08-28
Clock: Rework clocks to avoid tick-to-cycle transformations
Andreas Hansson
2012-08-28
Port: Stricter port bind/unbind semantics
Andreas Hansson
2012-08-28
Checker: Fix checker CPU ports
Andreas Hansson
2012-08-27
Ruby: Remove RubyEventQueue
Nilay Vaish
2012-08-22
Packet: Remove NACKs from packet and its use in endpoints
Andreas Hansson
2012-08-21
CPU: Remove overloaded function_trace_start parameter
Andreas Hansson
2012-08-21
Clock: Make Tick unsigned and remove UTick
Andreas Hansson
2012-08-21
Clock: Move the clock and related functions to ClockedObject
Andreas Hansson
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