Age | Commit message (Collapse) | Author |
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--HG--
extra : convert_revision : 7542f130b269a6a09e6ed51ae4689d1faa45a155
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is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.
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extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
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the time it was repsonded to. In timing mode the
time it was responded to is curTick. Doesn't change the results, but it does make implementation of nextCycle() more difficult
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extra : convert_revision : 67ed6261a5451d17d96d5df45992590acc353afc
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No need to initialize memory contents; should come up as 0.
src/cpu/memtest/memtest.cc:
No need to initialize memory contents; should come up as 0.
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extra : convert_revision : 1713676956f3d33b4686fee2650bd17027bcc495
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Make code compatible with new decode method.
src/arch/alpha/remote_gdb.cc:
src/cpu/base_dyn_inst_impl.hh:
src/cpu/exetrace.cc:
src/cpu/simple/base.cc:
Make code compatible with new decode method.
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
Modified instruction decode method.
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extra : convert_revision : a9a6d3a16fff59bc95d0606ea344bd57e71b8d0a
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extra : convert_revision : 8af0dd9c16e7db8ed92f7a71c396841d5ae7e072
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"moreBytes" which just takes a MachInst.
src/arch/x86/predecoder.cc:
Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes.
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extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : 1d2efac895a1c8328026a079e0b319a436325616
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src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
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extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f
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real thing. Also rename the null case to something that can
be a C++ symbol.
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--HG--
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bit in the ExtMachInst.
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--HG--
extra : convert_revision : 3953ace8d481d758d6e0d89183c0a7e7bebcf681
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
src/cpu/simple/base.cc:
Hand merge
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extra : convert_revision : a2902ef9d917d22ffb9c7dfa2fd444694a65240d
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into zamp.eecs.umich.edu:/.automount/greenville/w/acolyte/newmem
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extra : convert_revision : c80b7ef5a2cc4ab1b86bb1eef7fae91886a7737d
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Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls.
exec tracing isn't needed for m5.fast binaries
Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead.
src/arch/sparc/miscregfile.cc:
Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead.
src/cpu/simple/base.cc:
Assign traceData to be NULL at BaseSimpleCPU constructor.
Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls.
exec tracing isn't needed for m5.fast binaries
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extra : convert_revision : 5dc92fff05c9bde994f1e0f1bb40e11c44eb72c6
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--HG--
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--HG--
extra : convert_revision : bccafe884e58a55b02ff408448e6644196e439a4
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the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
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rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
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into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86
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extra : convert_revision : 276d00a73b1834d5262129c3f7e0f7fae18e23bc
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--HG--
extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
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and schedules the event immediately.
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extra : convert_revision : a84e729a5ef3632cbe6cff858c453c782707d983
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into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86
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extra : convert_revision : 3f17fc418ee5a30da2b08a515fb394cc8fcdd237
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--HG--
extra : convert_revision : cf68886d53301e0a63705247bd7d66b2ff08ea84
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extra : convert_revision : 56f6f2cbf4e92b7f2dd8c9453831fab86d83ef80
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it always returns true and nacks the packet if there isn't sufficient buffer space
fix the timing cpu to handle receiving a nacked packet
src/cpu/simple/timing.cc:
make the timing cpu handle receiving a nacked packet
src/mem/bridge.cc:
src/mem/bridge.hh:
the bridge never returns false when recvTiming() is called on its ports now, it always returns true and nacks the packet if there isn't sufficient buffer space
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extra : convert_revision : 5e12d0cf6ce985a5f72bcb7ce26c83a76c34c50a
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--HG--
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extra : convert_revision : 8cc2943ebc41e4d430789ee7923dd0dc878be06b
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head
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extra : convert_revision : 11df5fb2a8f1fa020d042e75b22a7f2f2bcbd9ab
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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extra : convert_revision : 05f738ab6cf1e8bd2940f4ce20602f1e8ad1af48
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src/cpu/o3/cpu.cc:
Use proper cycles for these equations.
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extra : convert_revision : cd49410eed978c789d788e80462abed6cb89fbae
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--HG--
extra : convert_revision : c82a62a61650e3700d237da917c453e5a9676320
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03cpu yet.
src/cpu/simple/base.cc:
Cpu's should start as unallocated, not suspended
src/cpu/simple_thread.cc:
Wait for a thread to be assigned to activate the cpu
src/kern/tru64/tru64.hh:
When looking for a open cpu to assign threads, look for an unallocated one, not a suspended one.
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extra : convert_revision : 5e3ad2e96b4a715ed38293ceaccff5b9f4ea7985
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--HG--
extra : convert_revision : c22907bed4b83f0dff51d2283dafe4f76fa9e94a
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gets it out of the cpu.
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extra : convert_revision : 20611263b799b5e835116adbf39d2ecc78701eef
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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--HG--
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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extra : convert_revision : a250eed999be9b8acd6f420fdfe8f1b02905beb1
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--HG--
extra : convert_revision : a1a218d3294515184689041487057495223360b7
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size than the architected one. Also fixed some asserts.
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extra : convert_revision : 26e7863919d1b976ba8cad747af475a6f18e9440
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IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
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extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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extra : convert_revision : 81269f094834f43b4e908321bfce2e031b39d2a4
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--HG--
extra : convert_revision : b02736c627bb9dcf87463a9133e04369b9f8fae2
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functions.
src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
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extra : convert_revision : 74f4b1f5fb6f95a56081f367cce7ff44acb5688a
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sized to match an IntReg which was what it used to be, but we might want to make it something architecture independent. All data is now endian converted before entering the store queue entries which simplifies store to load forwarding in "trans endian" simulations, and makes twin memory ops work.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
fixed twin memory operations.
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extra : convert_revision : 8fb97f98e285cd22413e06e146fa82392ac2a590
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--HG--
extra : convert_revision : 89eff82642ff181a9b95c77c4d2bf620ca837113
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