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path: root/src/cpu
AgeCommit message (Expand)Author
2011-02-18inorder: add valid bit for resource requestsKorey Sewell
2011-02-18inorder: remove reqRemoveListKorey Sewell
2011-02-18inorder: initialize res. req. vectors based on resource bandwidthKorey Sewell
2011-02-12inorder: clean up the old way of inst. schedulingKorey Sewell
2011-02-12inorder: utilize cached skeds in pipelineKorey Sewell
2011-02-12inorder: define iterator for resource schedulesKorey Sewell
2011-02-12inorder: stage scheduler for front/back end schedule creationKorey Sewell
2011-02-12inorder: cache instruction schedulesKorey Sewell
2011-02-12inorder: comments for resource sked classKorey Sewell
2011-02-12inorder: remove unused fileKorey Sewell
2011-02-11O3: Fix pipeline restart when a table walk completes in the fetch stage.Giacomo Gabrielli
2011-02-11SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk o...Ali Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06TimingSimpleCPU: split data sender state fixJoel Hestness
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
2011-02-04inorder: fault handlingKorey Sewell
2011-02-04inorder: pcstate and delay slots bugKorey Sewell
2011-02-04inorder: add a fetch buffer to fetch unitKorey Sewell
2011-02-04inorder: overload find-req fnKorey Sewell
2011-02-04inorder: implement separate fetch unitKorey Sewell
2011-02-04inorder: cache port blockingKorey Sewell
2011-02-04inorder: stage width as a python parameterKorey Sewell
2011-02-04inorder: multi-issue branch resolutionKorey Sewell
2011-02-04inorder: pipe. stage inst. bufferingKorey Sewell
2011-02-04inorder: change skidBuffer to list instead of queueKorey Sewell
2011-02-04inorder: activity tracking bugKorey Sewell
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-02-02O3: Fix a style bug in O3.Gabe Black
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
2011-01-18O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.Matt Horsnell
2011-01-18O3: Don't test misprediction on load instructions until executed.Matt Horsnell
2011-01-18O3: Keep around the last committed instruction and use for squashing.Ali Saidi
2011-01-18O3: Don't try to scoreboard misc registers.Ali Saidi
2011-01-18O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.Matt Horsnell
2011-01-18O3: Fix mispredicts from non control instructions.Matt Horsnell
2011-01-18O3: Fixes the way prefetches are handled inside the iew unit.Matt Horsnell
2011-01-18O3: Support timing translations for O3 CPU fetch.Ali Saidi
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2011-01-18O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.Min Kyu Jeong
2011-01-12inorder: fix RUBY_FS buildKorey Sewell
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2011-01-07inorder: replace schedEvent() code with reschedule().Steve Reinhardt
2011-01-07inorder: get rid of references to mainEventQueue.Steve Reinhardt
2011-01-03Move sched_list.hh and timebuf.hh from src/base to src/cpu.Steve Reinhardt
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
2010-12-22This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh f...Nilay Vaish
2010-12-21memtest: delete some crufty dead codeSteve Reinhardt
2010-12-20Style: Replace some tabs with spaces.Gabe Black