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path: root/src/cpu
AgeCommit message (Expand)Author
2014-01-29cpu: fix bug when TrafficGen deschedules eventXiangyu Dong
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2014-01-24checker: CheckerCPU handling of MiscRegs was incorrectGeoffrey Blake
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
2014-01-24cpu: Add support for Memory+Barrier instruction types in O3 cpu.Giacomo Gabrielli
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24base: add support for probe points and common probesMatt Horsnell
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2014-01-24cpu: Relax check on squashed non-speculative instructionsAndreas Hansson
2014-01-24cpu: remove faulty simpoint basic block inst count assertionDam Sunwoo
2013-12-03cpu: call BaseCPU startup() function in o3 cpuNilay Vaish
2013-10-15kvm: Set the perf exclude_host attribute if availableAndreas Sandberg
2013-11-26kvm: Remove the unused hostFreq member from BaseKvmCPUAndreas Sandberg
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
2013-11-15cpu: Fix Checker register index useAndreas Hansson
2013-10-31cpu: Construct ROB with cpu params struct instead of each variableFaissal Sleiman
2013-10-31cpu: Fix O3 issuse with load+barrier instructions.Ali Saidi
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-17cpu: Removing an unused variable in renameFaissal Sleiman
2013-10-17cpu: Change IEW DPRINTF to use IEW debug flagFaissal Sleiman
2013-10-17cpu: Put in assertions to check for maximum supported LQ/SQ sizeFaissal Sleiman
2013-10-17cpu: Fix O3 uncacheable load that is replayed but misses the TLBAli Saidi
2013-10-16kvm: Fix latency calculation of IPR accessesAndreas Sandberg
2013-10-15arch/x86: add support for explicit CC register fileYasuko Eckert
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu/o3: clean up rename map and free listSteve Reinhardt
2013-10-15cpu: rename *_DepTag constants to *_Reg_BaseSteve Reinhardt
2013-10-15cpu/o3: clean up scoreboard objectSteve Reinhardt
2013-10-15cpu/o3: clean up physical register fileSteve Reinhardt
2013-10-15cpu/inorder: merge register class enumsSteve Reinhardt
2013-10-15cpu: clean up architectural register classificationSteve Reinhardt
2013-10-03kvm: Service events in the instruction event queuesAndreas Sandberg
2013-09-30kvm: Add support for thread-specific instruction eventsAndreas Sandberg
2013-09-30kvm: FPU synchronization support on x86Andreas Sandberg
2013-09-30kvm: x86: Fix segment registers to make them VMX compatibleAndreas Sandberg
2013-09-25kvm: Add x86 segment register verification to help debuggingAndreas Sandberg
2013-09-25kvm: Initial x86 supportAndreas Sandberg
2013-09-19kvm: Correctly handle the return value from handleIpr(Read|Write)Andreas Sandberg
2013-09-19kvm: Fix a case where the run timers weren't armed properlyAndreas Sandberg
2013-09-11cpu: Dynamically instantiate O3 CPU LSQUnitsJoel Hestness
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-09-04cpu: Move the branch predictor out of the BaseCPUAndreas Hansson
2013-09-04arch: Header clean up for NOISA resurrectionAndreas Hansson
2013-08-20cpu: Fix timing CPU isDrained comment formattingAndreas Hansson
2013-08-19cpu: Accurately count idle cycles for simple cpuLena Olson
2013-08-19cpu: Fix TrafficGen trace playbackSascha Bischoff
2013-08-19cpu: Fix timing CPU drain checkAndreas Hansson
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