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2010-10-24O3: Get rid of a bunch of commented out lines.Gabe Black
2010-10-04Alpha: Fix Alpha NumMiscArchRegs constant.Gabe Black
Also add asserts in O3's Scoreboard class to catch bad indexes.
2010-09-30CPU/Cache: Fix some errors exposed by valgrindAli Saidi
2010-09-20CPU: Fix O3 and possible InOrder segfaults in FS.Gabe Black
2010-09-14CPU: Trim unnecessary includes from some common files.Gabe Black
This reduces the scope of those includes and makes it less likely for there to be a dependency loop. This also moves the hashing functions associated with ExtMachInst objects to be with the ExtMachInst definitions and out of utility.hh.
2010-09-13CPU: Get rid of the now unnecessary getInst/setInst family of functions.Gabe Black
This code is no longer needed because of the preceeding change which adds a StaticInstPtr parameter to the fault's invoke method, obviating the only use for this pair of functions.
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2010-08-31CPU: Get rid of the unused ev5_trap function on the simple and checker CPUs.Gabe Black
2010-08-25memtest: fix/cleanup functional access testingSteve Reinhardt
Don't assert that the response packet is marked as a response since it won't always be so for functional accesses. Also cleanup code to refer to functional accesses rather than "probes" (old terminology), and mention in the DPRINTF which type of access we're doing.
2010-08-25CPU: Print out traces for faluting inst when the flag ExecFaulting is setAli Saidi
2010-08-25ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)Min Kyu Jeong
When decoding a srs instruction, invalid mode encoding returns invalid instruction. This can happen when garbage instructions are fetched from mispredicted path
2010-08-24testers: move testers to a new directoryBrad Beckmann
This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. --HG-- rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
2010-08-23ISA: Get rid of old, unused utility functions cluttering up the ISAs.Gabe Black
2010-08-23CPU: Make the constants for StaticInst flags visible outside the class.Gabe Black
2010-08-23O3: Skipping mem-order violation check for uncachable loads.Min Kyu Jeong
Uncachable load is not executed until it reaches the head of the ROB, hence cannot cause one.
2010-08-23ARM: Improve printing of uop disassembly.Min Kyu Jeong
2010-08-23CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflagMin Kyu Jeong
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory ↵Min Kyu Jeong
instructions
2010-08-23ARM: mark msr/mrs instructions as SerializeBefore/AfterMin Kyu Jeong
Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR
2010-08-23O3: Handle loads when the destination is the PC.Min Kyu Jeong
For loads that PC is the destination, check if the load was mispredicted again when the value being loaded returns from memory
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false.
2010-08-23CPU: Set a default value when readBytes faults.Ali Saidi
This was being done in read(), but if readBytes was called directly it wouldn't happen. Also, instead of setting the memory blob being read to -1 which would (I believe) require using memset with -1 as a parameter, this now uses bzero. It's hoped that it's more specialized behavior will make it slightly faster.
2010-08-20ruby: Fixed minor bug in ruby test for setting the request typeBrad Beckmann
2010-08-20ruby: Resurrected Ruby's deterministic testsBrad Beckmann
Added the request series and invalidate deterministic tests as new cpu models and removed the no longer needed ruby tests --HG-- rename : configs/example/rubytest.py => configs/example/determ_test.py rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/DirectedGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/DirectedGenerator.hh rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/InvalidateGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/InvalidateGenerator.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/directedtest/RubyDirectedTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/directedtest/RubyDirectedTester.hh rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/SeriesRequestGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/SeriesRequestGenerator.hh
2010-08-20memtest: Memtester support for DMABrad Beckmann
This patch adds DMA testing to the Memtester and is inherits many changes from Polina's old tester_dma_extension patch. Since Ruby does not work in atomic mode, the atomic mode options are removed.
2010-08-14Inorder: Fix compilation of m5.fast.Gabe Black
printMemData is only used in DPRINTFs. If those are removed by compiling m5.fast, that function is unused, gcc generates a warning, that gets turned into an error, and the build fails. This change surrounds the function definition with #if TRACING_ON so it only gets compiled in if the DPRINTFs do to.
2010-08-13Merge with head.Gabe Black
2010-08-13CPU: Add readBytes and writeBytes functions to the exec contexts.Gabe Black
2010-08-13InOrder: Clean up some DPRINTFs that print data sent to/from the cache.Gabe Black
2010-08-13CPU: Tidy up endianness handling for mmapped "IPR"s.Gabe Black
2010-08-12TimingSimpleCPU: fix NO_ACCESS memory op handlingJoel Hestness
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs to handle the case where the current status of the CPU is Running and not DcacheWaitResponse or DTBWaitResponse
2010-07-22LSQ Unit: After deleting part of a split request, set it to NULL so that itTimothy M. Jones
isn't accidentally deleted again later (causing a segmentation fault).
2010-07-22O3CPU: Fix a bug where stores in the cpu where never marked as split.Timothy M. Jones
2010-07-22O3CPU: O3's tick event gets squashed when it is switched out. When repeatedlyTimothy M. Jones
switching between O3 and another CPU, O3's tick event might still be scheduled in the event queue (as squashed). Therefore, check for a squashed tick event as well as a non-scheduled event when taking over from another CPU and deal with it accordingly.
2010-06-28inorder: remove another debug statKorey Sewell
2010-06-26inorder: remove debugging statKorey Sewell
m5 doesnt do stats specific to binary and this resource request stat is probably only useful for people who really know the ins/outs of the model anyway
2010-06-25inorder: Return Address Stack bugKorey Sewell
the nextPC was getting sent to the branch predictor not the current PC, so the RAS was returning the wrong PC and mispredicting everything.
2010-06-25inorder: resource scheduling backendKorey Sewell
replace priority queue with vector of lists(1 list per stage) and place inside a class so that we have more control of when an instruction uses a particular schedule entry ... also, this is the 1st step toward making the InOrderCPU fully parameterizable. See the wiki for details on this process
2010-06-24inorder: cleanup virtual functionsKorey Sewell
remove the annotation 'virtual' from function declaration that isnt being derived from
2010-06-24inorder: enforce 78-character ruleKorey Sewell
2010-06-24inorder: exe_unit_stats for resolved branchesKorey Sewell
2010-06-23inorder: squash from memory stallKorey Sewell
this applies to multithreading models which would like to squash a thread on memory stall
2010-06-23inorder: record load/store trace dataKorey Sewell
2010-06-23inorder: update branch predictorKorey Sewell
- use InOrderBPred instead of Resource for DPRINTFs - account for DELAY SLOT in updating RAS and in squashing - don't let squashed instructions update the predictor - the BTB needs to use the ASID not the TID to work for multithreaded programs - add stats for BTB hits
2010-06-23inorder-stats: add instruction type statsKorey Sewell
also, remove inst-req stats as default.good for debugging but in terms of pure processor stats they aren't useful
2010-06-23inorder: stall signal handlingKorey Sewell
remove stall only when necessary add debugging printfs
2010-06-23inorder: tick schedulingKorey Sewell
use nextCycle to calculate ticks after addition
2010-06-23O3ThreadContext: When taking over from a previous context, only assert thatTimothy M. Jones
the system pointers match in Full System mode.
2010-06-14stats: get rid of the never-really-used event stuffNathan Binkert
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