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cpu
Age
Commit message (
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Author
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2011-01-07
inorder: replace schedEvent() code with reschedule().
Steve Reinhardt
2011-01-07
inorder: get rid of references to mainEventQueue.
Steve Reinhardt
2011-01-03
Move sched_list.hh and timebuf.hh from src/base to src/cpu.
Steve Reinhardt
2011-01-03
Make commenting on close namespace brackets consistent.
Steve Reinhardt
2010-12-22
This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh f...
Nilay Vaish
2010-12-21
memtest: delete some crufty dead code
Steve Reinhardt
2010-12-20
Style: Replace some tabs with spaces.
Gabe Black
2010-12-07
O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).
Ali Saidi
2010-12-07
O3: Support squashing all state after special instruction
Ali Saidi
2010-12-07
O3: Make all instructions that write a misc. register not perform the write u...
Giacomo Gabrielli
2010-12-07
O3: Support SWAP and predicated loads/store in ARM.
Min Kyu Jeong
2010-12-07
ARM: Support switchover with hardware table walkers
Ali Saidi
2010-12-01
ruby: Converted old ruby debug calls to M5 debug calls
Nilay Vaish
2010-11-23
X86: Loosen an assert for x86 and connect the APIC ports when caches are used.
Gabe Black
2010-11-19
SCons: Support building without an ISA
Ali Saidi
2010-11-18
O3: Fix fp destination register flattening, and index offset adjusting.
Gabe Black
2010-11-15
O3: Make O3 support variably lengthed instructions.
Gabe Black
2010-11-15
O3: reset architetural state by calling clear()
Ali Saidi
2010-11-15
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
Giacomo Gabrielli
2010-11-15
O3: prevent a squash when completeAcc() modifies misc reg through TC.
Min Kyu Jeong
2010-11-15
SCons: Cleanup SCons output during compile
Ali Saidi
2010-11-15
CPU: Fix bug when a split transaction is issued to a faster cache
Ali Saidi
2010-11-08
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
Ali Saidi
2010-11-08
ARM: Make all ARM uops delayed commit.
Ali Saidi
2010-11-08
sim: Use forward declarations for ports.
Ali Saidi
2010-10-31
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
Gabe Black
2010-10-24
O3: Get rid of a bunch of commented out lines.
Gabe Black
2010-10-04
Alpha: Fix Alpha NumMiscArchRegs constant.
Gabe Black
2010-09-30
CPU/Cache: Fix some errors exposed by valgrind
Ali Saidi
2010-09-20
CPU: Fix O3 and possible InOrder segfaults in FS.
Gabe Black
2010-09-14
CPU: Trim unnecessary includes from some common files.
Gabe Black
2010-09-13
CPU: Get rid of the now unnecessary getInst/setInst family of functions.
Gabe Black
2010-09-13
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
Gabe Black
2010-09-10
style: fix sorting of includes and whitespace in some files
Nathan Binkert
2010-08-31
CPU: Get rid of the unused ev5_trap function on the simple and checker CPUs.
Gabe Black
2010-08-25
memtest: fix/cleanup functional access testing
Steve Reinhardt
2010-08-25
CPU: Print out traces for faluting inst when the flag ExecFaulting is set
Ali Saidi
2010-08-25
ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)
Min Kyu Jeong
2010-08-24
testers: move testers to a new directory
Brad Beckmann
2010-08-23
ISA: Get rid of old, unused utility functions cluttering up the ISAs.
Gabe Black
2010-08-23
CPU: Make the constants for StaticInst flags visible outside the class.
Gabe Black
2010-08-23
O3: Skipping mem-order violation check for uncachable loads.
Min Kyu Jeong
2010-08-23
ARM: Improve printing of uop disassembly.
Min Kyu Jeong
2010-08-23
CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflag
Min Kyu Jeong
2010-08-23
CPU: Make Exec trace to print predication result (if false) for memory instru...
Min Kyu Jeong
2010-08-23
ARM: mark msr/mrs instructions as SerializeBefore/After
Min Kyu Jeong
2010-08-23
O3: Handle loads when the destination is the PC.
Min Kyu Jeong
2010-08-23
ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.
Min Kyu Jeong
2010-08-23
CPU: Set a default value when readBytes faults.
Ali Saidi
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