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2006-07-07Fix for bug when draining and a memory access is outstanding.Kevin Lim
--HG-- extra : convert_revision : 1af782cf023ae74c2a3ff9f7aefcea880bc87936
2006-07-07Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : e8933f852352164f4e50444f94cc6ee260e06766
2006-07-07Switch out fixes for CPUs.Kevin Lim
src/cpu/o3/cpu.cc: Fix up keeping proper state when switched out and drained. src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Keep track of the event we use to schedule fetch initially and upon resume. We may have to cancel the event if the CPU is switched out. --HG-- extra : convert_revision : 60a2a1bd2cdc67bd53ca4a67aa77166c826a4c8c
2006-07-07Remove hack now that ports work properlyRon Dreslinski
--HG-- extra : convert_revision : 43c22294867d7cbbc67ae66ec41a1d1c89f5a59d
2006-07-07Update cpus to use the getPort function to use a connector object to connect ↵Ron Dreslinski
the I/D cache ports to memory configs/test/test.py: Update to use new cpu getPort functionality src/cpu/base.cc: Make cpu's a memObject to expose getPort interface src/cpu/base.hh: Make cpu's a memObject to export getPort interface src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Now use the connector via getPort interface src/mem/cache/base_cache.cc: Make sure the cache recognizes all port names --HG-- extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
2006-07-06Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 942c43e2fdd68cde7aaaba5e88a667f80feab162
2006-07-06Support serializing and unserializing in the O3 CPU. Also a few small fixes ↵Kevin Lim
for draining/switching CPUs. src/cpu/o3/commit_impl.hh: Fix to clear drainPending variable on call to resume. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Support serializing and unserializing in the O3 CPU. src/cpu/o3/lsq_impl.hh: Be sure to say we have no stores to write back if the active thread list is empty. src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: Slightly change how SimpleThread is used to copy from other ThreadContexts. --HG-- extra : convert_revision : 92a5109b3783a989d5b451036061ef82c56d3121
2006-07-06Fix the O3CPU to support the multi-pass method for checking if the system ↵Kevin Lim
has fully drained. src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: Return a value so that the CPU can instantly return from draining if the pipeline is already drained. src/cpu/o3/cpu.cc: Use values returned from pipeline stages so that the CPU can instantly return from draining if the pipeline is already drained. --HG-- extra : convert_revision : d8ef6b811644ea67c8b40c4719273fa224105811
2006-07-06Various serialization changes to make it possible for the O3CPU to checkpoint.Kevin Lim
src/arch/alpha/regfile.hh: Define serialize/unserialize functions on MiscRegFile itself. src/cpu/o3/regfile.hh: Remove old commented code. src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: Push common serialization code to ThreadState level. Also allow the SimpleThread to be used for checkpointing by other models. src/cpu/thread_state.cc: src/cpu/thread_state.hh: Move common serialization code into ThreadState. --HG-- extra : convert_revision : ef64ef515355437439af967eda2e610e8c1b658b
2006-07-06Timing cache works for hello world test.Ron Dreslinski
Still need 1) detailed CPU (blocking ability in cache) 1a) Multiple outstanding requests (need to keep track of times for events) 2)Multi-level support 3)MP coherece support 4)LL/SC support 5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu)) src/cpu/simple/timing.cc: Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port. src/mem/cache/base_cache.cc: Handle marking MSHR's in service Add support for getting CSHR's src/mem/cache/base_cache.hh: Make these functions visible at the base cache level src/mem/cache/cache.hh: make the functions virtual src/mem/cache/cache_impl.hh: Rename the function to make sense src/mem/packet.hh: Accidentally clearing the needsResponse field when sending a response back. --HG-- extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2
2006-07-06Fixes for draining.Kevin Lim
src/cpu/simple/timing.cc: Update for changed return values. src/python/m5/__init__.py: Loop in order to make sure all objects are really drained. Objects may become undrained as other objects become drained (e.g. a bus-bridge has a packet, while a bus is empty, and the first drain() will cause the bus-bridge to give the packet to the bus). The only case we know every object is actually drained is if they all return immediately that they are drained. --HG-- extra : convert_revision : 80057a1d6d30381bd0b67b23549bd202f447c5cb
2006-07-06Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 00f8eecf99c771ae8943ed1d3a652bfbcfe1c6bc
2006-07-06Support for draining, and the new method of switching out. Now switching ↵Kevin Lim
out happens after the pipeline has been drained, deferring the three way handshake to the normal drain mechanism. The calls of switchOut() and takeOverFrom() both take action immediately. src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: Support for draining, new method of switching out. --HG-- extra : convert_revision : 05bf8b271ec85b3e2c675c3bed6c42aeba21f465
2006-07-06Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ↵Korey Sewell
ALPHA_ISA"... wierd but OK --HG-- extra : convert_revision : f847d6c01212e32200a319c16596b8e1c1d15c7d
2006-07-06Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : 2f08ea52ef54118d42aa590c0d86aa0cc7988713
2006-07-06Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a ↵Korey Sewell
specific ISA dyn. inst. src/cpu/cpu_models.py: Use O3DynInst src/cpu/o3/dyn_inst.hh: declare O3DynInst here based off of ISA ... this must be updated for each ISA. src/cpu/static_inst.hh: take out O3 forward declarations here and include header file to keep this file clean --HG-- extra : convert_revision : 0d65463479c3cfc2d1154935b1032dae32c5efd0
2006-07-06more steps toward O3 SMTKorey Sewell
src/arch/mips/isa/formats/fp.isa: Adjust for newmem src/cpu/cpu_models.py: Use O3DynInst instead of convoluted way src/cpu/o3/alpha/impl.hh: take out O3DynInst typedef here ... src/cpu/o3/cpu.cc: open up the SMT functions in the O3CPU src/cpu/static_inst.hh: Add O3DynInst src/cpu/o3/dyn_inst.hh: Use to get ISA-specific O3DynInst --HG-- extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
2006-07-05Remove sampler and serializer. Now they are handled through C++ interacting ↵Kevin Lim
with Python. src/SConscript: src/cpu/base.cc: src/cpu/base.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/sim/pseudo_inst.cc: Remove sampler. src/sim/sim_object.cc: Remove serializer. --HG-- extra : convert_revision : ce7616189440f3dc70040148da6d07309a386008
2006-07-05Rename quiesce to drain to avoid confusion with the pseudo instruction.Kevin Lim
src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/python/m5/__init__.py: src/python/m5/config.py: src/sim/main.cc: src/sim/sim_events.cc: src/sim/sim_events.hh: src/sim/sim_object.cc: src/sim/sim_object.hh: Rename quiesce to drain. --HG-- extra : convert_revision : fc3244a3934812e1edb8050f1f51f30382baf774
2006-07-05Checker ignores any faults that occur in syscall emulation mode for now.Kevin Lim
src/cpu/checker/cpu_impl.hh: The only fault we handle in SE causes troubles when invoked with the Checker. This is because it changes state within the process, and not the checker, so the state isn't correct when the main CPU calls invoke. It's safe to just ignore the fault in the Checker and continue. --HG-- extra : convert_revision : 5000d763a75009c7a6011646a6790ac5b23df6bb
2006-07-05Fix up some merge problems.Kevin Lim
src/base/traceflags.py: Remove BaseCPU traceflag. src/cpu/o3/alpha/params.hh: Move non-Alpha specific parameters out of this params class. src/cpu/o3/params.hh: Move non-Alpha specific params into this params class. --HG-- extra : convert_revision : e5b652adb47a240376733400e6054c66c50bd514
2006-07-05Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge src/base/traceflags.py: src/cpu/SConscript: Hand merge. src/cpu/o3/alpha/params.hh: Hand merge. This needs to get changed. --HG-- rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py extra : convert_revision : 581f338f5bce35288f7d15d95cbd0ac3a9135e6a
2006-07-05Need to change state upon quiescing.Kevin Lim
--HG-- extra : convert_revision : 25e3b0a463a0191cab9290665409d0abca6a179a
2006-07-05Split off files that are shared across the O3 and Ozone models.Kevin Lim
--HG-- extra : convert_revision : 023e84660d5cee5162d39548f87e5ca8ec68115f
2006-07-05Add some different parameters. The main change is that the writeback count ↵Kevin Lim
is now limited so that it doesn't overflow the buffer. src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_params.hh: Add in dispatchWidth, wbWidth, wbDepth parameters. wbDepth is the number of cycles of wbWidth instructions that can be buffered. src/cpu/o3/iew.hh: Include separate parameter for dispatch width. Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed. The IQ must make sure with the IEW stage that it can issue instructions prior to issuing. src/cpu/o3/iew_impl.hh: Include separate parameter for dispatch width. Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed. src/cpu/o3/inst_queue_impl.hh: IQ needs to check with the IEW to make sure it can issue instructions, and increments the IEW wb counter each time there is an outstanding instruction that will writeback. src/cpu/o3/lsq_unit_impl.hh: Be sure to decrement the writeback counter if there's a squashed load that returned. src/python/m5/objects/AlphaO3CPU.py: Change the parameters to include dispatch width, writeback width, and writeback depth. --HG-- extra : convert_revision : 31c8cc495273e3c481b79055562fc40f71291fc4
2006-07-05Fix some unset values in the request in the timing CPU.Ron Dreslinski
Properly implement the MSHR allocate function. src/cpu/simple/timing.cc: Set the thread context in the CPU. Need to do this properly, currently I just set it to Cpu=0 Thread=0. This will just cause all the stats in the cache based on these to just yield totals and not a distribution. src/mem/cache/miss/mshr.cc: Properly implement the allocate function for the MSHR. --HG-- extra : convert_revision : bcece518e54ed1404db3196f996a77b4dd5c1c1e
2006-07-03Fix for FS O3CPU compile ... missing forward class declaration/header file ↵Korey Sewell
after files got split for ISA-independence src/cpu/o3/alpha/thread_context.hh: Use 'this' when accessing cpu src/cpu/o3/cpu.hh: add numActiveThreds function src/cpu/o3/thread_context.hh: forward class declarations src/cpu/o3/thread_context_impl.hh: add quiesce event header file src/cpu/thread_context.hh: add exit() function to thread context (read comments in file) src/sim/syscall_emul.cc: adjust exitFunc syscall --HG-- extra : convert_revision : 323dc871e2b4f4ee5036be388ceb6634cd85a83e
2006-07-02typo ... change 'single_thread' to 'round_robin_policy'Korey Sewell
--HG-- extra : convert_revision : a4a5cb90557f786d42c6178bc6e268312c5ecbee
2006-07-02Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)Korey Sewell
Edit Test3 for newmem src/base/traceflags.py: Add O3CPU flag src/cpu/base.cc: for some reason adding a BaseCPU flag doesnt work so just go back to old way... src/cpu/o3/alpha/cpu_builder.cc: Determine number threads by workload size instead of solely by parameter. Default SMT fetch policy to RoundRobin if it's not specified in Config file src/cpu/o3/commit.hh: only use nextNPC for !ALPHA src/cpu/o3/commit_impl.hh: add FetchTrapPending as condition for commit src/cpu/o3/cpu.cc: panic if active threads is more than Impl::MaxThreads src/cpu/o3/fetch.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: name stuff src/cpu/o3/fetch_impl.hh: fatal if try to use SMT branch count, that's unimplemented right now src/python/m5/config.py: make it clearer that a parameter is not valid within a configuration class --HG-- extra : convert_revision : 55069847304e40e257f9225f0dc3894ce6491b34
2006-07-01traceflag stuffKorey Sewell
src/base/traceflags.py: add BaseCPU flag, O3CPUAll flag grouping src/cpu/base.cc: Use BaseCPU flag instead of FullCPU flag --HG-- extra : convert_revision : 32f737a2f58eb936634799f1f809e07cbba90179
2006-07-01fix cpu builder to build the correct name...Korey Sewell
add activateThread event and functions src/cpu/o3/alpha/cpu_builder.cc: Have CPU builder build a DerivO3CPU not a DerivAlphaO3CPU src/cpu/o3/cpu.cc: add activateThread Event add activateThread function adjust activateContext to schedule a thread to activate within the CPU instead of activating thread right away. This will lead to stages trying to use threads that arent ready yet and wasting execution time & possibly performance. src/cpu/o3/cpu.hh: add activateThread Event add activateThread function add schedule/descheculed activate thread event --HG-- extra : convert_revision : 236d30dc160910507ad36f7f527ab185ed38dc04
2006-06-30Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : 3c1405d8b4831c6240e02ba65a72043ca55f4a46
2006-06-30now O3CPU is totally independent of the ISA... all alpha specific stuff is ↵Korey Sewell
the cpu/o3/alpha directory src/cpu/o3/alpha/cpu.cc: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/impl.hh: filenames src/cpu/o3/alpha/thread_context.hh: public src/cpu/o3/base_dyn_inst.cc: src/cpu/o3/bpred_unit.cc: src/cpu/o3/commit.cc: src/cpu/o3/cpu.cc: src/cpu/o3/decode.cc: src/cpu/o3/fetch.cc: src/cpu/o3/iew.cc: src/cpu/o3/inst_queue.cc: src/cpu/o3/lsq.cc: src/cpu/o3/lsq_unit.cc: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/rename.cc: src/cpu/o3/rob.cc: use O3CPUImpl ... not Alpha src/cpu/o3/checker_builder.cc: filename --HG-- extra : convert_revision : 6eb739909699ade1e2a9d63637b182413ceebc69
2006-06-30Make O3CPU model independent of the ISAKorey Sewell
Use O3CPU when building instead of AlphaO3CPU. I could use some better python magic in the cpu_models.py file! AUTHORS: add middle initial SConstruct: change from AlphaO3CPU to O3CPU src/cpu/SConscript: edits to build O3CPU instead of AlphaO3CPU src/cpu/cpu_models.py: change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model... Actually, some Python expertise could be used here. The 'env' variable is not passed to this file, so I had to parse through the ARGV to find the ISA... src/cpu/o3/base_dyn_inst.cc: src/cpu/o3/bpred_unit.cc: src/cpu/o3/commit.cc: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/decode.cc: src/cpu/o3/fetch.cc: src/cpu/o3/iew.cc: src/cpu/o3/inst_queue.cc: src/cpu/o3/lsq.cc: src/cpu/o3/lsq_unit.cc: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/rename.cc: src/cpu/o3/rob.cc: use isa_specific.hh src/sim/process.cc: only initi NextNPC if not ALPHA src/cpu/o3/alpha/cpu.cc: alphao3cpu impl src/cpu/o3/alpha/cpu.hh: move AlphaTC to it's own file src/cpu/o3/alpha/cpu_impl.hh: Move AlphaTC to it's own file ... src/cpu/o3/alpha/dyn_inst.cc: src/cpu/o3/alpha/dyn_inst.hh: src/cpu/o3/alpha/dyn_inst_impl.hh: include paths src/cpu/o3/alpha/impl.hh: include paths, set default MaxThreads to 2 instead of 4 src/cpu/o3/alpha/params.hh: set Alpha Specific Params here src/python/m5/objects/O3CPU.py: add O3CPU class src/cpu/o3/SConscript: include isa-specific build files src/cpu/o3/alpha/thread_context.cc: NEW HOME of AlphaTC src/cpu/o3/alpha/thread_context.hh: new home of AlphaTC src/cpu/o3/isa_specific.hh: includes ISA specific files src/cpu/o3/params.hh: base o3 params src/cpu/o3/thread_context.hh: base o3 thread context src/cpu/o3/thread_context_impl.hh: base o3 thead context impl --HG-- rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e
2006-06-30AtomicSimpleCPU with a cache now runs the hello world! test program.Ron Dreslinski
Need to clean up a bunch of flags/hacks in the code. Then onto Timming mode. Functional accesses also work properly, although not exactly how we wanted them. I'll need to clean that up as well. src/cpu/simple/atomic.cc: Atomic CPU needs to set thread context so stats work in cache. Temporarily just use CPU=0 ThreadID=0 src/mem/cache/cache_impl.hh: Need to return success/failure properly still Physical memory object doesn't assert SATISFIED anymore, need to remove that flag src/mem/cache/tags/lru.cc: Doesn't work if the REQ doesn't set it's ASID. Temporary fix use 0 always --HG-- extra : convert_revision : d06a39684af593db699b64df9a29f80c61d8d050
2006-06-29Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 0756f7f1f63fae472e0ef1d20e9eb38e56de78c8
2006-06-29Various fixes for the CPU models to support the features that have been ↵Kevin Lim
moved to python. src/cpu/base.cc: src/cpu/base.hh: src/cpu/simple/atomic.hh: Switching out no longer takes a sampler. src/cpu/simple/atomic.cc: Fix up switching out. Also fix up serialization; the nameOut() was messing up the ordering. src/cpu/simple/timing.cc: Add in quiesce, fix up serialization. src/cpu/simple/timing.hh: Add in queisce, fix up serialization. --HG-- extra : convert_revision : 9d59d53bdf269d4d82fb119e5ae7c8a5d475880b
2006-06-27Make full CPU handle SE faultsAli Saidi
--HG-- extra : convert_revision : e336623ac3329ec0ee2430548c6a9650e2a69d6a
2006-06-26Merge zizzer:/bk/newmemAli Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 39c99c8acadd43f3ec42ae7550289a5075d910e4
2006-06-26don't depend on the memory system to return the atomic cpu a multiple of cpu ↵Ali Saidi
cycles. --HG-- extra : convert_revision : e5eb36f14c8394381a0269fefd34a178833c8346
2006-06-26add syscall emulation page table fault so we can allocate more stack pagesAli Saidi
src/cpu/simple/base.cc: add syscall emulation page table fault so we can allocate more stack pages FaultBase::invoke will do this, we don't need to do it here src/sim/faults.hh: I have no idea why this #if was there... gone src/sim/process.cc: make stack_min actually be the current minimum --HG-- extra : convert_revision : 9786b39f2747b94654a5d77c74243cd20503add4
2006-06-25Make OzoneCPU work again in SE/FS.Kevin Lim
src/cpu/ozone/cpu.hh: Fixes to get OzoneCPU working in SE/FS again. src/cpu/ozone/cpu_impl.hh: Be sure to set up ports properly. src/cpu/ozone/front_end.hh: Allow port to be created without specifying its name at the beginning. src/cpu/ozone/front_end_impl.hh: Setup port properly, also only use checker if it's enabled. src/cpu/ozone/lw_back_end_impl.hh: Be sure to initialize variables. src/cpu/ozone/lw_lsq.hh: Handle locked flag for UP systems. src/cpu/ozone/lw_lsq_impl.hh: Initialize all variables. src/python/m5/objects/OzoneCPU.py: Fix up config. --HG-- extra : convert_revision : c99e7bf82fc0dd1099c7a82eaebd58ab6017764d
2006-06-22Checker related updates.Kevin Lim
src/cpu/o3/cpu.cc: Updates to make sure the checker is compiled in if enabled and also to include it only when it's used. --HG-- extra : convert_revision : c48ead5b2665dc858acd87c2ee99d39d80594a69
2006-06-22Changes to get OzoneCPU to compile once more.Kevin Lim
The changes largely are fixing up the memory accesses to use ports/Requests/Packets, supporting the splitting off of instantiation of template classes, and handling some of the reorganization that happened. OzoneCPU is untested for now but at least compiles. Fixes will be coming shortly. SConstruct: Remove OzoneSimpleCPU from list of CPUs. src/cpu/SConscript: Leave out OzoneSimpleCPU. src/cpu/ozone/bpred_unit.cc: Fixes to get OzoneCPU to compile. src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/dyn_inst.hh: src/cpu/ozone/dyn_inst_impl.hh: src/cpu/ozone/front_end.cc: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/ozone_impl.hh: src/cpu/ozone/rename_table.cc: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: Fixes to get OzoneCPU back to compiling. --HG-- extra : convert_revision : 90ffb397263bcf9fea3987317272c64f2b20f7e6
2006-06-22Change ThreadState constructor ordering to match the rest of the ThreadStates.Kevin Lim
--HG-- extra : convert_revision : 63d98aa8b6a694c285d95a2a57e1b3aaef4cee3b
2006-06-22Misc fixes.Kevin Lim
src/cpu/o3/alpha_dyn_inst_impl.hh: Consolidate these calls into one. src/cpu/o3/commit_impl.hh: Include checker only if it's being used. src/cpu/o3/fetch_impl.hh: Do not deallocate request if it's a squashed response that was received. src/cpu/o3/lsq_unit.hh: Add in comment. src/cpu/o3/lsq_unit_impl.hh: Only include checker if it's being used. --HG-- extra : convert_revision : aae0bf1e19baae90f1e61d41191548612bbb3be6
2006-06-22Split Checker up properly into templated and non-templated definitions.Kevin Lim
--HG-- extra : convert_revision : 3ead18e42f4a536f2f868da07cb81a8940a7fa2f
2006-06-22Fix to have the static inst exec sigs also dependent on the CPU models used.Kevin Lim
--HG-- extra : convert_revision : 65d978d638dd9a57a641ca52adcf2c0ef48edf1c
2006-06-17Minor updates.Kevin Lim
src/cpu/o3/alpha_cpu.hh: Fix #define in header. util/rundiff: Fix file comments to be more correct. util/tracediff: Update comments to be more correct. --HG-- extra : convert_revision : a28030ce8979de3d9361191c6af23743460dc53e
2006-06-17Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 037fe9ee54da7e11c2bd07388b9f79cda9abef4c
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 11:03:02 +0000