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AgeCommit message (Collapse)Author
2008-06-18AtomicSimpleCPU: Separate data stalls from instruction stalls.Nathan Binkert
Separate simulation of icache stalls and dat stalls.
2008-06-17ThreadState: Ensure that kernelStats is properly initializedNathan Binkert
2008-06-15port: Clean up default port setup and port switchover code.Nathan Binkert
2008-06-12CPU: Make the simple cpu trace data for loads/stores.Gabe Black
2008-04-10SCons: add comments to SConscript documenting bug workaroundAli Saidi
--HG-- extra : convert_revision : e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3
2008-04-08SCons: Manually specifying header only directories with Dir() works around ↵Ali Saidi
the problem --HG-- extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3
2008-03-24Don't FastAlloc MSHRs since we don't allocate them on the fly.Steve Reinhardt
--HG-- extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
2008-03-06O3CPU: Don't call dumpInsts if DEBUG is not definedVilas Sridharan
--HG-- extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245
2008-02-27Add comments in code to describe bug conditions.Korey Sewell
This should help if somebody gets to the bug fix before me (or someone else)... --HG-- extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
2008-02-27Fix Load/Store Queue squashing after a SMT thread is removed but ensuringKorey Sewell
you are squashing from the current instruction # causing the thread exit. --HG-- extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
2008-02-27Fix offset in removeThread() function so that float registers start freeing upKorey Sewell
from the right point (#32 usually) instead of restarting at 0 and double-freeing. Commented out assert line in free_list.hh that will check for when double-free condition goes bad. --HG-- extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
2008-02-26TLB: Make a TLB base class and put a virtual demapPage function in it.Gabe Black
--HG-- extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
2008-02-14CPU: move the PC Events code to a place where the code won't be executed ↵Ali Saidi
multiple times if an instruction faults. --HG-- extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
--HG-- extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
2008-02-06Make the Event::description() a const functionStephen Hines
--HG-- extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
2008-02-05Add base ARM code to M5Stephen Hines
--HG-- extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
2008-01-14The reason is that the event is supposed to put the instructions ready to ↵Ke Meng
execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. Signed-off by: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
2008-01-02Add ReadRespWithInvalidate to handle multi-level coherence situationSteve Reinhardt
where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. --HG-- extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
--HG-- extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
--HG-- extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
2007-12-18Checkpointing: Fix a bug in the simulation script when restoring without ↵Ali Saidi
standard switch and change some ifs to work with the default port since every port is now connected to something. --HG-- extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
2007-12-16CPU: Update where the simple cpus read their cpu id from the thread context ↵Ali Saidi
to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations. --HG-- extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
2007-11-21imported patch pagewalker.patchGabe Black
--HG-- extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f
2007-11-20Simple CPU fix simple mistake in translateDataWriteAddr.Gabe Black
--HG-- extra : convert_revision : 6a6a7d05f62d9d9868be0707e4dc186a5f7ecf7d
2007-11-15add thread id to misc. reg functionsKorey Sewell
--HG-- extra : convert_revision : 35d073d1279947d943a0290832e09a5268dd0b76
2007-11-15add MicroPC functions back to thread contextKorey Sewell
--HG-- extra : convert_revision : a9cfd2829c4aec191f5f9ec6ce7b5d1dccc92af1
2007-11-15add microPC stuff back in. got deleted on changeset propragation somehow.Korey Sewell
--HG-- extra : convert_revision : 5e89484b2ef21457ffba35ef959df999a28c5676
2007-11-15put the flattenIndex stuff back in O3 AND put fatal() back in faultsKorey Sewell
--HG-- extra : convert_revision : 16fb8d7f3fbc5f8f1fc3ed34427c3d90a3125ad0
2007-11-15add core specific parameter to BaseCPU paramsKorey Sewell
--HG-- extra : convert_revision : 15c5995e3acf23a45c712891fd06ef273584f7e8
2007-11-15Get MIPS simple regression working. Take out unecessary functions ↵Korey Sewell
"setShadowSet", "CacheOp" --HG-- extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea
2007-11-15branch mergeKorey Sewell
--HG-- extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
--HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
2007-11-12X86: Separate out the page table walker into it's own cc and hh.Gabe Black
--HG-- extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042
2007-11-12X86: Work on the page table walker, TLB, and related faults.Gabe Black
--HG-- extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
2007-11-12X86: Implement a page table walker.Gabe Black
--HG-- extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
2007-11-12X86: Make the micropc available through the thread context objects.Gabe Black
This is necssary for fault handlers that branch to non-zero micro PCs. --HG-- extra : convert_revision : c1cb4863d779a9f4a508d0b450e64fb7a985f264
2007-11-08TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.Ali Saidi
--HG-- extra : convert_revision : a305cf9dcaca5ed3b97499a5e24c511f4416125a
2007-11-08AtomicSimpleCPU: Refactor resume() code to have a cleaner control path.Ali Saidi
--HG-- extra : convert_revision : f27bb96850e7fb0252fb1f47c3d0860705c32884
2007-11-08Interrupts: Inline some code and remove duplication.Ali Saidi
--HG-- extra : convert_revision : 0631c601f281bdd2a12ff0d0ae94576780115c2a
2007-11-08CPU: Add function to explictly compare thread contexts after copying.Ali Saidi
--HG-- extra : convert_revision : 9b7af59a11202a91409aad7c427b7749cd1d2f12
2007-11-06O3: Remove unneeded variable.Gabe Black
--HG-- extra : convert_revision : 4624ccd3f08818f4632881d6aca6d1cc343bbdcf
2007-10-31String constant const-ness changes to placate g++ 4.2.Steve Reinhardt
Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). --HG-- extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one ↵Ali Saidi
file with them all. --HG-- extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-10-22CPU: Add functions to the "ExecContext"s that translate a given address.Gabe Black
--HG-- extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397
2007-10-18CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.Ali Saidi
--HG-- extra : convert_revision : 6d025764682181b1f67df3b1d8d1d59099136df7
2007-10-02Merge with head.Gabe Black
--HG-- extra : convert_revision : 1aa0e4569a7c10e6a395c2c951ac29275b5bcf59
2007-10-02Predecoder: Clear out predecoder state on an ITLB fault.Gabe Black
--HG-- extra : convert_revision : 68f8ff778dbd28ade5070edf5a7d662e7bf0045a
2007-10-02CPU: Make the cpuid parameter get set in SE mode as well.Gabe Black
--HG-- extra : convert_revision : bc47206acb683ebaaa31f57af79b4b8db64e4d31
2007-10-02CPU: Make the cpus check the pc event queues in SE mode.Gabe Black
--HG-- extra : convert_revision : 9dc4ea136c3c3f87a73d55e91bc4aae4eba70464
2007-10-02CPU: Make sure the system parameter gets set in the cpu builders. Other ↵Gabe Black
parameters need to be fixed as well. --HG-- extra : convert_revision : 0401970a79855ee0a96eb29305346ce07b5c98ea
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