Age | Commit message (Collapse) | Author |
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impression that this code is ISA independent.
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extra : convert_revision : 67d9e51702efbe5f5244268e3753328a6cf1a1d5
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src/arch/alpha/faults.hh:
Only use pagetable.hh in FS
src/arch/alpha/pagetable.hh:
pagetable.hh should only be included in FS, so protecting it internally should be unnecessary.
src/cpu/exetrace.cc:
Only use tlb.hh in FS
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extra : convert_revision : 91ea61f2e7970e7146b6d407ee250fcb20cd4d48
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : e4f9bb663099662a94c5522e6b4955c2a83bac8d
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use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?
src/arch/sparc/faults.cc:
set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
fix endian issues with condition codes
src/arch/sparc/tlb.hh:
add implemented physical addres constants
src/arch/sparc/utility.hh:
add tlb.hh to utilities
src/base/loader/raw_object.cc:
add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
use memcpy instead of bcopy
src/cpu/exetrace.cc:
clean up printing a bit more
src/cpu/m5legion_interface.h:
add tons to the shared interface
src/dev/ethertap.cc:
s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
hack to make sure htole() works...
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extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
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extra : convert_revision : b3e9fa094d68f608865dedfc9f3f4125a20fd748
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than sprintf which was breaking on 64 bit hosts.
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extra : convert_revision : 184d751392dfcc8c80ac1a6c0ebc3061ff0a3f20
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bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
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extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0
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extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : 29426cebe81ac077c1a83f50e914ff6955ce81d4
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--HG--
extra : convert_revision : 1626703583f02a1c9823874290462c1b6bdb6c3c
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rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc
rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh
rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc
rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh
rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh
rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc
rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh
extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966
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--HG--
extra : convert_revision : b3f956af92cb98b4945aebc8aece1dffcabdf15c
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src/python/m5/main.py:
add option to operate in lockstep with legion
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extra : convert_revision : 2cc90ec0cf7e8d028ee813c2034a77415671a628
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extra : convert_revision : a4c4195bc07383149a56907f26d327a4bfa77c26
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src/cpu/o3/mem_dep_unit_impl.hh:
Initialize mem dep unit properly, add debug output.
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extra : convert_revision : 3c56dedfa57de1edc4b1c8f8d9bc94e18002eff2
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extra : convert_revision : cd07a920417b7fb34e5ca3bf70d707327eb59eb3
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extra : convert_revision : 7b58f75e5efc3c9ead2434f87605cbabcb23d90a
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base kernel_stats to base_kernel_stats
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extra : convert_revision : 2a010d2eb7ea2586ff063b99b8bcde6eb1e8e017
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/SConscript:
SCCS merged
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extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
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but isn't tested. Other architectures will not.
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extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
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src/cpu/base.cc:
Move clock phase drift code to the base CPU so that any CPU model can use it.
src/cpu/base.hh:
Added two functions to help get the next cycle the CPU should be scheduled.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Use the function now in BaseCPU.
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extra : convert_revision : 444494b66ffc85fc473c23f57683c5f9458ad80c
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src/cpu/o3/lsq_unit_impl.hh:
Be sure to initialize pointer to NULL.
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extra : convert_revision : 917d5119e4bd8eae10959ed07069d8c694315c7a
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : d7133e32cfca9f15869ee9ab7a93e3470e7d9038
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SConstruct:
Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
solaris doesn't have random(), so use rint with the correct rounding mode
if we're compiling on solaris
src/base/stats/flags.hh:
u_int32_t??
src/base/time.hh:
grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
we don't need to include stdint here
src/sim/byteswap.hh:
the method to detect endianness on Solaris is a little more complex...
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extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1
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can access it.
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extra : convert_revision : bd836d63ac3630b20dda552e7b289730f3c114ef
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are in PAL mode, however.
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extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
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records when interrupts are requested, and returns an interrupt to execute if the
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extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
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src/cpu/simple_thread.cc:
Fix up port handling to share code.
src/cpu/thread_state.cc:
Separate code off into a function.
src/cpu/thread_state.hh:
Make a separate function that will get the CPU's memory's functional port.
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extra : convert_revision : 96a9bb3c5e4b9ba5511678c0fd17f0017c8cd312
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src/cpu/simple_thread.cc:
This function should have been deleted from an earlier push.
src/cpu/simple_thread.hh:
Delete this function; it's now in thread_state.hh/.cc.
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extra : convert_revision : f78dcf9c2b388418030d48d0ea4911c8b8b1f5ff
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src/arch/alpha/utility.hh:
For now makeExtMI will be specific to the ISA.
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extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
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file functions to not take faults
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extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 88fa7ae5cc32be068787ee381fae9d8de0e9bd0f
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
Hand merge.
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extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
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for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
No need for mem parameter any more.
src/cpu/checker/cpu.cc:
Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
Remove memory parameter.
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extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
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src/cpu/simple/atomic.hh:
Port now takes in the MemObject that owns it.
src/cpu/simple/timing.hh:
Port now takes in MemObject that owns it.
src/dev/io_device.cc:
src/mem/bus.hh:
Ports now take in the MemObject that owns it.
src/mem/cache/base_cache.cc:
Ports now take in the MemObject that own it.
src/mem/port.hh:
src/mem/tport.hh:
Ports now optionally take in the MemObject that owns it.
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extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
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--HG--
extra : convert_revision : 581f97dafc2b30bd5067f6ff7f9cdbabc6890622
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functions.
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extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
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more neutral names.
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extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
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src/cpu/simple/base.cc:
Make a microcoded op start at the current micropc, rather than starting at 0.
src/cpu/thread_state.cc:
Serialize the microPC and nextMicroPC
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extra : convert_revision : 5302215f17312ecef3ff4c6548acb05297ee4ff6
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extra : convert_revision : aad1ee04ade9f4394c9ef0386f23d6f2ca373412
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extra : convert_revision : 4762b8ab46ac755726cc658a378c2cf5b2061dc3
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extra : convert_revision : b2d505de51fc5fcae5177b2a13140729474e249e
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 30a912cf5d3f205a6301d291dd1799da21663056
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
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