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Age
Commit message (
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Author
2011-02-04
inorder: change skidBuffer to list instead of queue
Korey Sewell
2011-02-04
inorder: activity tracking bug
Korey Sewell
2011-02-03
Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.
Gabe Black
2011-02-03
Config: Keep track of uncached and cached ports separately.
Gabe Black
2011-02-02
O3: Fix a style bug in O3.
Gabe Black
2011-02-01
X86: Add L1 caches for the TLB walkers.
Gabe Black
2011-01-18
O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.
Matt Horsnell
2011-01-18
O3: Don't test misprediction on load instructions until executed.
Matt Horsnell
2011-01-18
O3: Keep around the last committed instruction and use for squashing.
Ali Saidi
2011-01-18
O3: Don't try to scoreboard misc registers.
Ali Saidi
2011-01-18
O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.
Matt Horsnell
2011-01-18
O3: Fix mispredicts from non control instructions.
Matt Horsnell
2011-01-18
O3: Fixes the way prefetches are handled inside the iew unit.
Matt Horsnell
2011-01-18
O3: Support timing translations for O3 CPU fetch.
Ali Saidi
2011-01-18
ARM: Add support for moving predicated false dest operands from sources.
Ali Saidi
2011-01-18
O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.
Min Kyu Jeong
2011-01-12
inorder: fix RUBY_FS build
Korey Sewell
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2011-01-07
inorder: replace schedEvent() code with reschedule().
Steve Reinhardt
2011-01-07
inorder: get rid of references to mainEventQueue.
Steve Reinhardt
2011-01-03
Move sched_list.hh and timebuf.hh from src/base to src/cpu.
Steve Reinhardt
2011-01-03
Make commenting on close namespace brackets consistent.
Steve Reinhardt
2010-12-22
This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh f...
Nilay Vaish
2010-12-21
memtest: delete some crufty dead code
Steve Reinhardt
2010-12-20
Style: Replace some tabs with spaces.
Gabe Black
2010-12-07
O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).
Ali Saidi
2010-12-07
O3: Support squashing all state after special instruction
Ali Saidi
2010-12-07
O3: Make all instructions that write a misc. register not perform the write u...
Giacomo Gabrielli
2010-12-07
O3: Support SWAP and predicated loads/store in ARM.
Min Kyu Jeong
2010-12-07
ARM: Support switchover with hardware table walkers
Ali Saidi
2010-12-01
ruby: Converted old ruby debug calls to M5 debug calls
Nilay Vaish
2010-11-23
X86: Loosen an assert for x86 and connect the APIC ports when caches are used.
Gabe Black
2010-11-19
SCons: Support building without an ISA
Ali Saidi
2010-11-18
O3: Fix fp destination register flattening, and index offset adjusting.
Gabe Black
2010-11-15
O3: Make O3 support variably lengthed instructions.
Gabe Black
2010-11-15
O3: reset architetural state by calling clear()
Ali Saidi
2010-11-15
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
Giacomo Gabrielli
2010-11-15
O3: prevent a squash when completeAcc() modifies misc reg through TC.
Min Kyu Jeong
2010-11-15
SCons: Cleanup SCons output during compile
Ali Saidi
2010-11-15
CPU: Fix bug when a split transaction is issued to a faster cache
Ali Saidi
2010-11-08
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
Ali Saidi
2010-11-08
ARM: Make all ARM uops delayed commit.
Ali Saidi
2010-11-08
sim: Use forward declarations for ports.
Ali Saidi
2010-10-31
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
Gabe Black
2010-10-24
O3: Get rid of a bunch of commented out lines.
Gabe Black
2010-10-04
Alpha: Fix Alpha NumMiscArchRegs constant.
Gabe Black
2010-09-30
CPU/Cache: Fix some errors exposed by valgrind
Ali Saidi
2010-09-20
CPU: Fix O3 and possible InOrder segfaults in FS.
Gabe Black
2010-09-14
CPU: Trim unnecessary includes from some common files.
Gabe Black
2010-09-13
CPU: Get rid of the now unnecessary getInst/setInst family of functions.
Gabe Black
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