Age | Commit message (Collapse) | Author |
|
formatting functions.
--HG--
extra : convert_revision : e3aa5919a6480aa01924c832a86fa1e8ddf5ba0d
|
|
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
|
|
configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.
--HG--
extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
|
|
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : 8d61b474428d494b1a5382e4cf95934ad54e35dd
|
|
src/cpu/simple/timing.cc:
Various updates for deleting requests more properly.
The major change is moving the deletion of the fetch request/packet to after the instruction has executed and completed. This should fix a few bugs because Ron's memory system didn't expect a call for a functional access while a timing access was being processed.
--HG--
extra : convert_revision : c7cf114bb1ff3cdaa7b0a40ed4c5302dc9d3a522
|
|
--HG--
extra : convert_revision : 7f082ba5c1cd2445aec731950c31a877aac23a75
|
|
src/cpu/simple/atomic.cc:
Make the atomic cpu return 0 on snoops.
--HG--
extra : convert_revision : aad96ad36e0c764c7cfef8b0c8e97877574f5845
|
|
--HG--
extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a
|
|
--HG--
extra : convert_revision : 40dfbb72c4e418c54e909c54dad5fe6ef7017cb4
|
|
--HG--
extra : convert_revision : 746bdf92334d220158eb0eb6bf113b4dcedbb354
|
|
--HG--
extra : convert_revision : 05db10e20d33302fe830d5759b8881b1233aca87
|
|
src/cpu/o3/fetch_impl.hh:
Fetch needs to make sure it isn't waiting on an Icache access.
--HG--
extra : convert_revision : b53eb58b9e5a00bdb394134586d1f84f84d1c6e1
|
|
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
--HG--
extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
|
|
--HG--
extra : convert_revision : 661b412b0ae670181b89cb7dbc5e9d813804aa7a
|
|
src/arch/alpha/interrupts.hh:
No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
Fix broken if statement from PcPAL updates, and properly populate the request fields.
Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
Populate request fields properly.
src/cpu/simple/base.cc:
Update for interrupt stuff.
--HG--
extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
|
|
the parameters to the BaseCPU object.
--HG--
extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e
|
|
impression that this code is ISA independent.
--HG--
extra : convert_revision : 67d9e51702efbe5f5244268e3753328a6cf1a1d5
|
|
src/arch/alpha/faults.hh:
Only use pagetable.hh in FS
src/arch/alpha/pagetable.hh:
pagetable.hh should only be included in FS, so protecting it internally should be unnecessary.
src/cpu/exetrace.cc:
Only use tlb.hh in FS
--HG--
extra : convert_revision : 91ea61f2e7970e7146b6d407ee250fcb20cd4d48
|
|
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : e4f9bb663099662a94c5522e6b4955c2a83bac8d
|
|
use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?
src/arch/sparc/faults.cc:
set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
fix endian issues with condition codes
src/arch/sparc/tlb.hh:
add implemented physical addres constants
src/arch/sparc/utility.hh:
add tlb.hh to utilities
src/base/loader/raw_object.cc:
add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
use memcpy instead of bcopy
src/cpu/exetrace.cc:
clean up printing a bit more
src/cpu/m5legion_interface.h:
add tons to the shared interface
src/dev/ethertap.cc:
s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
hack to make sure htole() works...
--HG--
extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
|
|
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
--HG--
extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
|
|
--HG--
extra : convert_revision : b3e9fa094d68f608865dedfc9f3f4125a20fd748
|
|
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
--HG--
extra : convert_revision : 56cb7fe3be5b63bd89b48ac6cb88b47d13b4c137
|
|
than sprintf which was breaking on 64 bit hosts.
--HG--
extra : convert_revision : 184d751392dfcc8c80ac1a6c0ebc3061ff0a3f20
|
|
bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
|
|
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
--HG--
extra : convert_revision : dafe2d4a032b277c219ea13faf20567c20c1f2f4
|
|
src/cpu/o3/cpu.cc:
Handle draining properly when CPU isn't actually being used.
src/cpu/simple/atomic.cc:
Be sure to set status properly when draining.
src/mem/bus.cc:
Fix for draining.
--HG--
extra : convert_revision : d9796e6693e974f022159029fc9743c49a970c8f
|
|
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
--HG--
extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0
|
|
--HG--
extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6
|
|
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
--HG--
extra : convert_revision : 29426cebe81ac077c1a83f50e914ff6955ce81d4
|
|
--HG--
extra : convert_revision : 1626703583f02a1c9823874290462c1b6bdb6c3c
|
|
--HG--
rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc
rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh
rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc
rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh
rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh
rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc
rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh
extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966
|
|
--HG--
extra : convert_revision : b3f956af92cb98b4945aebc8aece1dffcabdf15c
|
|
src/python/m5/main.py:
add option to operate in lockstep with legion
--HG--
extra : convert_revision : 2cc90ec0cf7e8d028ee813c2034a77415671a628
|
|
--HG--
extra : convert_revision : a4c4195bc07383149a56907f26d327a4bfa77c26
|
|
src/cpu/o3/mem_dep_unit_impl.hh:
Initialize mem dep unit properly, add debug output.
--HG--
extra : convert_revision : 3c56dedfa57de1edc4b1c8f8d9bc94e18002eff2
|
|
--HG--
extra : convert_revision : cd07a920417b7fb34e5ca3bf70d707327eb59eb3
|
|
--HG--
extra : convert_revision : 7b58f75e5efc3c9ead2434f87605cbabcb23d90a
|
|
base kernel_stats to base_kernel_stats
--HG--
extra : convert_revision : 2a010d2eb7ea2586ff063b99b8bcde6eb1e8e017
|
|
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/SConscript:
SCCS merged
--HG--
extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
|
|
but isn't tested. Other architectures will not.
--HG--
extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
|
|
src/cpu/base.cc:
Move clock phase drift code to the base CPU so that any CPU model can use it.
src/cpu/base.hh:
Added two functions to help get the next cycle the CPU should be scheduled.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Use the function now in BaseCPU.
--HG--
extra : convert_revision : 444494b66ffc85fc473c23f57683c5f9458ad80c
|
|
src/cpu/o3/lsq_unit_impl.hh:
Be sure to initialize pointer to NULL.
--HG--
extra : convert_revision : 917d5119e4bd8eae10959ed07069d8c694315c7a
|
|
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : d7133e32cfca9f15869ee9ab7a93e3470e7d9038
|
|
SConstruct:
Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
solaris doesn't have random(), so use rint with the correct rounding mode
if we're compiling on solaris
src/base/stats/flags.hh:
u_int32_t??
src/base/time.hh:
grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
we don't need to include stdint here
src/sim/byteswap.hh:
the method to detect endianness on Solaris is a little more complex...
--HG--
extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1
|
|
can access it.
--HG--
extra : convert_revision : bd836d63ac3630b20dda552e7b289730f3c114ef
|
|
are in PAL mode, however.
--HG--
extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
|
|
records when interrupts are requested, and returns an interrupt to execute if the
--HG--
extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
|
|
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
--HG--
extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
|
|
src/cpu/simple_thread.cc:
Fix up port handling to share code.
src/cpu/thread_state.cc:
Separate code off into a function.
src/cpu/thread_state.hh:
Make a separate function that will get the CPU's memory's functional port.
--HG--
extra : convert_revision : 96a9bb3c5e4b9ba5511678c0fd17f0017c8cd312
|