gem5 - gem5

Age	Commit message (Expand)	Author
2009-07-29	Simple CPU: Make the simple CPU handle the IntRegs trace flag.	Gabe Black
2009-07-27	ARM: Make native trace print out what instruction caused an error.	Gabe Black
2009-07-25	o3-smt: enforce numThreads parameter for SMT SE mode	Korey Sewell
2009-07-19	CPU: Separate out native trace into ISA (in)dependent code and SimObjects.	Gabe Black
2009-07-08	Get rid of the unused get(Data\|Inst)Asid and (inst\|data)Asid functions.	Gabe Black
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
2009-07-08	Registers: Eliminate the ISA defined RegFile class.	Gabe Black
2009-07-08	Registers: Move the PCs out of the ISAs and into the CPUs.	Gabe Black
2009-07-08	ARM, Simple CPU: Fix an index and add assert checks.	Gabe Black
2009-07-08	Registers: Eliminate the ISA defined integer register file.	Gabe Black
2009-07-08	Registers: Eliminate the ISA defined floating point register file.	Gabe Black
2009-07-08	Registers: Get rid of the float register width parameter.	Gabe Black
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2009-06-04	move: put predictor includes and cc files into the same place	Nathan Binkert
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-05-17	includes: sort includes again	Nathan Binkert
2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
2009-05-12	cpus: add InOrderCPU to default build	Korey Sewell
2009-05-12	inorder-resources: delete events	Korey Sewell
2009-05-12	inorder-tlb-cunit: merge the TLB as implicit to any memory access	Korey Sewell
2009-05-12	inorder-tlb: squash insts in TLB correctly	Korey Sewell
2009-05-12	inorder-faults: ignore unalign translation faults for prefetches	Korey Sewell
2009-05-12	inorder-stc: update interface to handle store conditionals	Korey Sewell
2009-05-12	inorder-float: Fix storage of FP results	Korey Sewell
2009-05-12	inorder-fetch: update model to use predecoder	Korey Sewell
2009-05-12	inorder-mem: clean up allocation/deletion of requests/packets	Korey Sewell
2009-05-12	inorder-mem: skeleton support for prefetch/writehints	Korey Sewell
2009-05-12	inorder-o3: allow both to compile together	Korey Sewell
2009-05-12	inorder-unified-tlb: use unified TLB instead of old TLB model	Korey Sewell
2009-05-12	inorder-miscregs: Fix indexing for misc. reg operands and update result-types...	Korey Sewell
2009-05-12	inorder/alpha-isa: create eaComp object visible to StaticInst through ISA	Korey Sewell
2009-05-12	inorder-bpred: edits to handle non-delay-slot ISAs	Korey Sewell
2009-05-12	inorder-alpha-port: initial inorder support of ALPHA	Korey Sewell
2009-05-05	cpus: fix cpu progress event	Korey Sewell
2009-04-21	arm: Unify the ARM tlb. We forgot about this when we did the rest.	Nathan Binkert
2009-04-20	request: rename INST_READ to INST_FETCH.	Steve Reinhardt
2009-04-19	Mem: Change isLlsc to isLLSC.	Gabe Black
2009-04-19	CPUs: Make the atomic CPU support locked memory accesses.	Gabe Black
2009-04-19	Memory: Rename LOCKED for load locked store conditional to LLSC.	Gabe Black
2009-04-19	CPU: If the simple CPU is already idle, just return from suspendContext, don'...	Gabe Black
2009-04-18	o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...	Korey Sewell
2009-04-17	o3, inorder: fix FS bug due to initializing ThreadState to Halted.	Steve Reinhardt
2009-04-15	o3: handle fetch with no active threads correctly.	Steve Reinhardt
2009-04-15	o3: fix {read,set}ArchFloatReg* functions.	Steve Reinhardt
2009-04-15	ThreadState: initialize status to Halted in constructor.	Steve Reinhardt
2009-04-15	Get rid of the Unallocated thread context state.	Steve Reinhardt
2009-04-08	tlb: More fixing of unified TLB	Nathan Binkert
2009-04-08	tlb: Don't separate the TLB classes into an instruction TLB and a data TLB	Gabe Black
2009-03-11	cpu: fix minor endian issue with trace output	Steve Reinhardt