summaryrefslogtreecommitdiff
path: root/src/cpu
AgeCommit message (Expand)Author
2007-04-02Remove/comment out DPRINTFs that were causing a segfault.Kevin Lim
2007-04-02Fix up SPARC's CPU builder to match changes to Alpha's CPU builder.Kevin Lim
2007-03-29Update code so that the O3 CPU can handle not initially having anything hooke...Kevin Lim
2007-03-24Update for new trace data behavior.Kevin Lim
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-23Updates for commit.Kevin Lim
2007-03-23Handle status bits a little better, as well as non-speculative instructions.Kevin Lim
2007-03-23Two fixes:Kevin Lim
2007-03-23Set progress_interval in terms of CPU cycles.Kevin Lim
2007-03-23A couple of minor fixes.Kevin Lim
2007-03-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-03-21The m5 side of statetrace. This is fairly ugly, but I don't want to lose it.Gabe Black
2007-03-18Compile fixes for SPARC_FS.Gabe Black
2007-03-16Fix ALPHA_FS compile. The MachInst -> StaticInstPtr constructor is no longer ...Gabe Black
2007-03-15Merge zizzer:/bk/newmemAli Saidi
2007-03-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-03-15Make the predecoder an object with it's own switched header file. Start addin...Gabe Black
2007-03-13fix segfault when peer owner attempts to use functional portAli Saidi
2007-03-13Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-03-13Replaced makeExtMI with predecode.Gabe Black
2007-03-13fix interrupting during a quisce on sparcAli Saidi
2007-03-12Merge zizzer:/bk/newmemRon Dreslinski
2007-03-12remove the extern C around gdb helper functions. It's need needed for any new...Ali Saidi
2007-03-12Fix some of the memory leaks related to writebacksRon Dreslinski
2007-03-11Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-03-11Make sttw and sttwa use the twin memory operations.Gabe Black
2007-03-10Rework the way SCons recurses into subdirectories, making itNathan Binkert
2007-03-10I thought this code got deleted, but since it hasn't I've moved it to a place...Ali Saidi
2007-03-09Two fixes:Kevin Lim
2007-03-08stop m5 from leaking like a sieveAli Saidi
2007-03-07I missed a couple of WithEffects, this should do itAli Saidi
2007-03-07Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-03-07*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscRegAli Saidi
2007-03-07Add setData functions for the new Twin??_t types.Gabe Black
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2007-03-05Add x86 version of call to "decode"Gabe Black
2007-03-05Added an x86 dyninstGabe Black
2007-03-03Merge zizzer:/bk/newmemAli Saidi
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
2007-03-02make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way a...Ali Saidi
2007-02-28Make trap instructions always generate TrapInstruction Fault objects which ca...Gabe Black
2007-02-17Give the progress event its own priorityNathan Binkert
2007-02-17Default to tracing being disabled in C++, it will be turnedNathan Binkert
2007-02-13Merge all of the execution trace configuration stuff intoNathan Binkert
2007-02-12some forgotten commitsAli Saidi
2007-02-12Merge zizzer:/bk/newmemAli Saidi
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2007-02-12Merge zizzer.eecs.umich.edu:/bk/newmemSteve Reinhardt
2007-02-12Move store conditional result checking from SimpleAtomicCpu writeSteve Reinhardt
2007-02-10Clean up tracing stuff more, get rid of the trace log sinceNathan Binkert
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 11:12:08 +0000