Age | Commit message (Collapse) | Author |
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the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
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--HG--
extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
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and schedules the event immediately.
--HG--
extra : convert_revision : a84e729a5ef3632cbe6cff858c453c782707d983
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--HG--
extra : convert_revision : 56f6f2cbf4e92b7f2dd8c9453831fab86d83ef80
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it always returns true and nacks the packet if there isn't sufficient buffer space
fix the timing cpu to handle receiving a nacked packet
src/cpu/simple/timing.cc:
make the timing cpu handle receiving a nacked packet
src/mem/bridge.cc:
src/mem/bridge.hh:
the bridge never returns false when recvTiming() is called on its ports now, it always returns true and nacks the packet if there isn't sufficient buffer space
--HG--
extra : convert_revision : 5e12d0cf6ce985a5f72bcb7ce26c83a76c34c50a
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--HG--
extra : convert_revision : 8a27ed80308c95988f3bc43d670dc0ac9e946d39
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--HG--
extra : convert_revision : 8cc2943ebc41e4d430789ee7923dd0dc878be06b
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head
--HG--
extra : convert_revision : 11df5fb2a8f1fa020d042e75b22a7f2f2bcbd9ab
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
--HG--
extra : convert_revision : 05f738ab6cf1e8bd2940f4ce20602f1e8ad1af48
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src/cpu/o3/cpu.cc:
Use proper cycles for these equations.
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extra : convert_revision : cd49410eed978c789d788e80462abed6cb89fbae
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--HG--
extra : convert_revision : c82a62a61650e3700d237da917c453e5a9676320
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03cpu yet.
src/cpu/simple/base.cc:
Cpu's should start as unallocated, not suspended
src/cpu/simple_thread.cc:
Wait for a thread to be assigned to activate the cpu
src/kern/tru64/tru64.hh:
When looking for a open cpu to assign threads, look for an unallocated one, not a suspended one.
--HG--
extra : convert_revision : 5e3ad2e96b4a715ed38293ceaccff5b9f4ea7985
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : c5275ef3e53393496a2ebe05b2f516884bb392f9
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--HG--
extra : convert_revision : cfebc877b9b2ebc8927ce8267867eb40ad6d59c6
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--HG--
extra : convert_revision : 70221349a7100c89be0d03210f3b04950370583f
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
--HG--
extra : convert_revision : a250eed999be9b8acd6f420fdfe8f1b02905beb1
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--HG--
extra : convert_revision : a1a218d3294515184689041487057495223360b7
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size than the architected one. Also fixed some asserts.
--HG--
extra : convert_revision : 26e7863919d1b976ba8cad747af475a6f18e9440
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IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
--HG--
extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
--HG--
extra : convert_revision : 81269f094834f43b4e908321bfce2e031b39d2a4
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--HG--
extra : convert_revision : b02736c627bb9dcf87463a9133e04369b9f8fae2
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functions.
src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
--HG--
extra : convert_revision : 74f4b1f5fb6f95a56081f367cce7ff44acb5688a
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sized to match an IntReg which was what it used to be, but we might want to make it something architecture independent. All data is now endian converted before entering the store queue entries which simplifies store to load forwarding in "trans endian" simulations, and makes twin memory ops work.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
fixed twin memory operations.
--HG--
extra : convert_revision : 8fb97f98e285cd22413e06e146fa82392ac2a590
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--HG--
extra : convert_revision : 89eff82642ff181a9b95c77c4d2bf620ca837113
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The removed ones were unnecessary. The commented out ones could be useful in the future, should this problem get fixed. See flyspray task #243.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
Remove/comment out DPRINTFs that were causing a segfault.
--HG--
extra : convert_revision : b5aeda1c6300dfde5e0a3e9b8c4c5f6fa00b9862
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--HG--
extra : convert_revision : ec2a739f1da07f0922c772e6998017995115ce80
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hooked up to its ports. This fixes the segfault Ali recently found when using sampling.
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
Update code so that the O3 CPU can handle not initially having anything hooked up to its ports.
--HG--
extra : convert_revision : 04bcef44e754735d821509ebd69b0ef9c8ef8e2c
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--HG--
extra : convert_revision : c3df20c5187614febc4cc9f4d4c68bfecfba1ea7
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
src/cpu/base_dyn_inst.hh:
Hand merge. Line is no longer needed because it's handled in the ISA.
--HG--
extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
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1. Move interrupt handling to a separate function to clean up main commit() function a bit. Also gate the function call off properly based on whether or not there are outstanding interrupts, and the system is not in PAL mode.
2. Better handling of updating instruction's status bits. Instructions are not marked "atCommit" until other stages view it (pushed off to IEW/IQ), and they have been properly handled (faults).
3. Don't consider the ROB "empty" for the purpose of other stages until the ROB is empty, all stores have written back, and there was no store commits this cycle. The last is necessary in case a store committed, in which case it would look like all stores have written back but in actuality have not.
src/cpu/o3/commit.hh:
Slightly modify how interrupts are handled. Also include some extra bools to keep track of state properly.
src/cpu/o3/commit_impl.hh:
Slightly modify how interrupts are handled. Also include some extra bools to keep track of state.
General correctness updates, most specifically for when commit broadcasts to other stages that the ROB is empty.
--HG--
extra : convert_revision : 682ec6ccf4ee6ed0c8a030ceaba1c90a3619d102
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src/cpu/o3/iew_impl.hh:
Allow for slightly more flexible handling of non-speculative instructions. They can be other classes now, such as loads or stores.
Also be sure to clear the state associated with squashes that are not used. i.e. if a squash due to a memory ordering violation happens on the same cycle as an older branch squashing, clear the state associated with the memory ordering violation.
Lastly don't consider uncached loads to officially be "at commit" until IEW receives the signal back from commit about the load.
src/cpu/o3/inst_queue_impl.hh:
Don't consider non-speculative instructions to be "at commit" until the IQ has received a signal from commit about the instruction. This prevents non-speculative instructions from being issued too early.
src/cpu/o3/mem_dep_unit_impl.hh:
Clear instruction's ability to issue if it's replayed.
--HG--
extra : convert_revision : d69dae878a30821222885485f4dee87170d56eb3
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1. Requests are handled more properly now. They assume the memory system takes control of the request upon sending out an access.
2. load-load ordering is maintained.
src/cpu/base_dyn_inst.hh:
Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out.
Also include some functions to allow certain status bits to be cleared.
src/cpu/base_dyn_inst_impl.hh:
Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out.
src/cpu/o3/fetch_impl.hh:
General correctness fixes. retryPkt is not necessarily always set, so handle it properly. Also consider the cache unblocked only when recvRetry is called.
src/cpu/o3/lsq_unit.hh:
Handle requests a little more correctly. Now that the requests aren't pointed to by the DynInst, be sure to delete the request if it's not being used by the memory system.
Also be sure to not store-load forward from an uncacheable store.
src/cpu/o3/lsq_unit_impl.hh:
Check to make sure load-load ordering was maintained.
Also handle requests a little more correctly.
--HG--
extra : convert_revision : e86bead2886d02443cf77bf7a7a1492845e1690f
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--HG--
extra : convert_revision : 76b0918276cb613eb314ab1479b5ffdb31f31dee
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1. Set CPU ID in all modes for the O3 CPU.
2. Use nextCycle() function to prevent phase drift in O3 CPU.
3. Remove assertion in rename map that is no longer true.
src/cpu/o3/alpha/cpu_builder.cc:
Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident.
src/cpu/o3/alpha/cpu_impl.hh:
Set the CPU ID properly.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces.
src/cpu/o3/rename_map.cc:
Remove assertion that is no longer true.
tests/configs/o3-timing.py:
Set CPU's id to 0.
--HG--
extra : convert_revision : 2b69c19adfce2adcc2d1939e89d702bd6674d5d5
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
--HG--
extra : convert_revision : 41214c71e7fa11d47395975a141793337d020463
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--HG--
extra : convert_revision : 171b41418567c1f41f43363a46fa9aeaa58ae606
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src/arch/alpha/predecoder.hh:
src/arch/sparc/predecoder.hh:
Put in a missing include
src/cpu/exetrace.cc:
Convert the legion lockstep stuff from makeExtMI to the predecoder object.
--HG--
extra : convert_revision : 91bad4466f8db1447fff8608fa46a5f236dc3a89
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a conversion constructor because it caused ambiguous conversions when setting the pointer to NULL.
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extra : convert_revision : ce9ecfc03a47642d105f2378208bbe923d6b765b
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 6a75fa02391c4c65063c5412a568705bb1dd892b
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
src/arch/mips/utility.hh:
src/arch/x86/SConscript:
Hand merge
--HG--
extra : convert_revision : 0ba457aab52bf6ffc9191fd1fe1006ca7704b5b0
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adding predecoding functionality to x86.
src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.
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extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
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--HG--
extra : convert_revision : 3702b4bd038a59bff823c3b428fdfbaabc9715df
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
--HG--
extra : convert_revision : 61eca737296a5ce839d3b97f047b4fda062cb899
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Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.
--HG--
extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
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src/arch/sparc/ua2005.cc:
fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to
check if were suspended and interrupt at the guess time
src/base/traceflags.py:
add trace flag for Iob
src/cpu/simple/base.cc:
Use Quisce instead of IPI trace flag
src/dev/sparc/iob.cc:
add some Dprintfs
--HG--
extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head
--HG--
extra : convert_revision : 7d7380a6565cff32470bddadb0158fad897a5cf5
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new version of gdb to work and it causes at least mine to segfault
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extra : convert_revision : 5e4c2ec753372fd0569734d3ddb0c8690409ca16
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src/cpu/memtest/memtest.cc:
Add the [] to a delete to make it work correctly
src/mem/cache/cache_impl.hh:
Fix one of the memory leaks
--HG--
extra : convert_revision : 64c7465c68a084efe38a62419205518b24d852a7
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
--HG--
extra : convert_revision : 725999a0a5bde6e065bad87b42e973c5c627c69f
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--HG--
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