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path: root/src/cpu
AgeCommit message (Expand)Author
2017-07-12kvm, mem: Refactor some Event subclasses into lambdasSean Wilson
2017-07-12cpu: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12cpu, sim: Add param to force CPUs to wait for GDBJose Marinho
2017-07-07kvm, arm: Don't forward IRQ/FIQ when using the kernel's GICAndreas Sandberg
2017-07-05arch: ISA parser additions of vector registersRekai Gonzalez-Alberquilla
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05cpu: Result refactoringRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05cpu: Physical register structural + flat indexingNathanael Premillieu
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2017-06-20cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2017-05-15cpu: fix problem with forwarding and locked loadAlec Roelke
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
2017-04-03arm, kvm: implement GIC state transferCurtis Dunham
2017-03-16cpu: Print progress messages in Trace CPURadhika Jagtap
2017-02-27syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess s...Brandon Potter
2015-07-20syscall_emul: [patch 13/22] add system call retry capabilityBrandon Potter
2017-02-14sim, kvm: make KvmVM a System parameterCurtis Dunham
2016-11-09style: [patch 3/22] reduce include dependencies in some headersBrandon Potter
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2017-01-03sim: Remove redundant export_method_cxx_predeclsAndreas Sandberg
2016-12-21cpu: implement an L-TAGE branch predictorArthur Perais
2016-12-21cpu: disallow speculative update of branch predictor tables (o3)Arthur Perais
2016-12-21cpu: correct comments in tournament branch predictorArthur Perais
2016-12-21cpu: Resolve targets of predicted 'taken' decode for O3Arthur Perais
2016-12-21cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3Arthur Perais
2016-12-05cpu: Change traffic generators to use different values for writesNikos Nikoleris
2016-11-30arch: [Patch 1/5] Added RISC-V base instruction set RV64IAlec Roelke
2016-11-30cpu: Remove branch predictor function predictInOrderJason Lowe-Power
2016-10-15cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClassFernando Endo
2016-10-06ruby: rename networktest to garnet_synthetic_traffic.Tushar Krishna
2016-09-22cpu: Fix the O3 CPU DrainRekai Gonzalez-Alberquilla
2016-09-15cpu: Support exit when any one Trace CPU completes replayRadhika Jagtap
2016-09-15cpu: Adjust for trace offset and fix statsRadhika Jagtap
2016-09-15cpu: Add frequency scaling to the Trace CPURadhika Jagtap
2016-09-13kvm: Support timing accesses for KVM cpuMichael LeBeane
2016-09-13sim: Refactor quiesce and remove FS assertsMichael LeBeane
2016-08-22cpu, mem, sim: Change how KVM maps memoryDavid Hashe
2016-08-15cpu: Add missing override in Minor's exec contextAndreas Sandberg
2016-08-15cpu: Fixed clang errors. Added 'override' keyword for virtual functions.Reiley Jeapaul
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-07-21cpu: Fix Minor SMT WFI/drain interaction issuesMitch Hayenga
2016-07-21cpu: Add SMT support to MinorCPUMitch Hayenga
2016-06-20mem: Resolve TrafficGen trace relative to the configAndreas Sandberg
2016-06-06pwr: Low-power idle power state for idle CPUsDavid Guillen Fandos
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-05-27cpu: fix lastStopped unserialisationIlias Vougioukas
2016-05-26cpu: Add a basic progress check to the TrafficGenAndreas Hansson
2016-04-07mem: Remove threadId from memory request classMitch Hayenga