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2011-08-19Fix bugs due to interaction between SEV instructions and O3 pipelineGeoffrey Blake
SEV instructions were originally implemented to cause asynchronous squashes via the generateTCSquash() function in the O3 pipeline when updating the SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system that would lead to a pipeline either going inactive indefinitely or not being able to commit squashed instructions. Fixed SEV instructions to behave like interrupts and cause synchronous sqaushes inside the pipeline, eliminating the race conditions. Also fixed up the semantics of the WFE instruction to behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1 or unmasked interrupts are pending.
2011-08-19LSQ: Add some better dprintfs for storeset predictor.Mrinmoy Ghosh
2011-08-19LSQ: Fix a few issues with the storeset predictor.Mrinmoy Ghosh
Two issues are fixed in this patch: 1. The load and store pc passed to the predictor are passed in reverse order. 2. The flag indicating that a barrier is inflight was never cleared when the barrier was squashed instead of committed. This made all load insts dependent on a non-existent barrier in-flight.
2011-08-19O3: Squash the violator and younger instructions instead not all insts.Giacomo Gabrielli
Change the way instructions are squashed on memory ordering violations to squash the violator and younger instructions, not all instructions that are younger than the instruction they violated (no reason to throw away valid work).
2011-08-16InOrder: Make cache_unit.hh include hashmap.hh explicitly, not transitively.Gabe Black
2011-08-16O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.Gabe Black
2011-08-14O3: When squashing, restore the macroop that should be used for fetching.Gabe Black
2011-08-14O3: Add a pointer to the macroop for a microop in the dyninst.Gabe Black
2011-08-13O3: At the end of an instruction, force fetchAddr to something sensible.Gabe Black
It's possible (though until now very unlikely) for fetchAddr to get out of sync with the actual PC of the current instruction. This change forcefull resets fetchAddr at the end of every instruction.
2011-08-09O3: Stop using the current macroop no matter why you're leaving it.Gabe Black
Until now, the only reason a macroop would be left was because it ended at a microop marked as the last microop. In O3 with branch prediction, it's possible for the branch predictor to have entries which originally came from different instructions which happened to have the same RIP. This could theoretically happen in many ways, but it was encountered specifically when different programs in different address spaces ran one after the other in X86_FS. What would happen in that case was that the macroop would continue to be looped over and microops fetched from it until it reached the last microop even though the macropc had moved out from under it. If things lined up properly, this could mean that the end bytes of an instruction actually fell into the instruction sized block of memory after the one in the predecoder. The fetch loop implicitly assumes that the last instruction sized chunk of memory processed was the last one needed for the instruction it just finished executing. It would then tell the predecoder to move to an offset within the bytes it was given that is larger than those bytes, and that would trip an assert in the x86 predecoder. This change fixes this problem by making fetch stop processing the current macroop if the address it should be fetching from changed when the PC is updated. That happens when the last microop was reached because the instruction handled it properly, and it also catches the case where the branch predictor makes fetch do a macro level branch when it shouldn't. The check of isLastMicroop is retained because otherwise, a macroop that branches back to itself would act like a single, long macroop instead of multiple instances of the same microop. There may be situations (which may turn out to be purely hypothetical) where that matters. This also fixes a relatively minor issue where the curMacroop variable would be set to NULL immediately after seeing that a microop was the last one before curMacroop was used to build the dyninst. The traceData structure would have a NULL pointer to the macroop for that microop.
2011-08-09O3: When waiting to handle an interrupt, let everything drain out.Gabe Black
Before this change, the commit stage would wait until the ROB and store queue were empty before recognizing an interrupt. The fetch stage would stop generating instructions at an appropriate point, so commit would then wait until a valid time to interrupt the instruction stream. Instructions might be in flight after fetch but not the in the ROB or store queue (in rename, for instance), so this change makes commit wait until all in flight instructions are finished.
2011-08-08BuildEnv: Eliminate RUBY as build environment variableNilay Vaish
This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled.
2011-08-07O3: Get rid of the unused addToRemoveList function.Gabe Black
2011-08-07O3: Let squashed and deferred instructions issue.Gabe Black
Let squahsed and deferred instructions issue so they don't accumulate and clog up the CPU.
2011-08-07O3: Fix uninitialized variable in the tournament branch predictor.Ali Saidi
2011-08-07Translation: Use a pointer type as the template argument.Gabe Black
This allows regular pointers and reference counted pointers without having to use any shim structures or other tricks.
2011-08-02O3: Get rid of the raw ExtMachInst constructor on DynInsts.Gabe Black
This constructor assumes that the ExtMachInst can be decoded directly into a StaticInst that's useful to execute. With the advent of microcoded instructions that's no longer true.
2011-07-31O3: Implement memory mapped IPRs for O3.Gabe Black
2011-07-30O3: Fix corner case squashing into the microcode ROM.Gabe Black
When fetching from the microcode ROM, if the PC is set so that it isn't in the cache block that's been fetched the CPU will get stuck. The fetch stage notices that it's in the ROM so it doesn't try to fetch from the current PC. It then later notices that it's outside of the current cache block so it skips generating instructions expecting to continue once the right bytes have been fetched. This change lets the fetch stage attempt to generate instructions, and only checks if the bytes it's going to use are valid if it's really going to use them.
2011-07-15O3: Create a pipeline activity viewer for the O3 CPU model.Giacomo Gabrielli
Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py) and modified O3 code base to support an extra trace flag (O3PipeView) for generating traces to be used as inputs by the tool.
2011-07-10Branch predictor: Fixes the tournament branch predictor.Mrinmoy Ghosh
Branch predictor could not predict a branch in a nested loop because: 1. The global history was not updated after a mispredict squash. 2. The global history was updated in the fetch stage. The choice predictors that were updated used the changed global history. This is incorrect, as it incorporates the state of global history after the branch in encountered. Fixed update to choice predictor using the global history state before the branch happened. 3. The global predictor table was also updated using the global history state before the branch happened as above. Additionally, parameters to initialize ctr and history size were reversed.
2011-07-10O3: Fix up pipelining icache accesses in fetch stage to function properlyGeoffrey Blake
Fixed up the patch from Yasuko Watanabe that enabled pipelining of fetch accessess to icache to work with recent changes to main repository. Also added in ability for fetch stage to delay issuing the fault carrying nop when a pipeline fetch causes a fault and no fetch bandwidth is available until the next cycle.
2011-07-10O3: Make sure fetch doesn't go off into the weeds during speculation.Ali Saidi
2011-07-02ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.Gabe Black
readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason.
2011-07-02ExecContext: Get rid of the now unused read/write templated functions.Gabe Black
2011-06-30Ruby: Add support for functional accessesBrad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch.
2011-06-20InOder: Fix a compile error.Gabe Black
2011-06-19inorder: clear reg. dep entry after removing from listKorey Sewell
this will safeguard future code from trying to remove from the list twice. That code wouldnt break but would waste time.
2011-06-19inorder: se: squash after syscallsKorey Sewell
2011-06-19inorder: cleanup dprintfs in cache unitKorey Sewell
2011-06-19inorder: SE mode TLB faultsKorey Sewell
handle them like we do in FS mode, by blocking the TLB until the fault is handled by the fault->invoke()
2011-06-19inorder:tracing: fix fault tracing bugKorey Sewell
2011-06-19inorder: se compile fixesKorey Sewell
2011-06-19inorder: add necessary debug flag header filesKorey Sewell
2011-06-19inorder: clear fetchbuffer on trapsKorey Sewell
implement clearfetchbufferfunction extend predecoder to use multiple threads and clear those on trap
2011-06-19inorder: use separate float-reg bits function in dyninstKorey Sewell
this will make sure we get the correct view of a FP register
2011-06-19inorder: use trapPending flag to manage trapsKorey Sewell
2011-06-19inorder/dtb: make sure DTB translate correct addressKorey Sewell
The DTB expects the correct PC in the ThreadContext but how if the memory accesses are speculative? Shouldn't we send along the requestor's PC to the translate functions?
2011-06-19inorder: handle serializing instructionsKorey Sewell
including IPR accesses and store-conditionals. These class of instructions will not execute correctly in a superscalar machine
2011-06-19inorder: dont handle multiple faults on same cycleKorey Sewell
if a faulting instruction reaches an execution unit, then ignore it and pass it through the pipeline. Once we recognize the fault in the graduation unit, dont allow a second fault to creep in on the same cycle.
2011-06-19inorder: register ports for FS modeKorey Sewell
handle "snoop" port registration as well as functional port setup for FS mode
2011-06-19inorder: check for interrupts each tickKorey Sewell
use a dummy instruction to facilitate the squash after the interrupts trap
2011-06-19inorder: explicit fault checkKorey Sewell
Before graduating an instruction, explicitly check fault by making the fault check it's own separate command that can be put on an instruction schedule.
2011-06-19inorder: squash and trap behind a tlb faultKorey Sewell
2011-06-19inorder: stall stores on store conditionals & compare/swapsKorey Sewell
2011-06-19inorder: make InOrder CPU FS compilable/visibleKorey Sewell
make syscall a SE mode only functionality copy over basic FS functions (hwrei) to make FS compile
2011-06-19inorder: remove memdep tracking for default pipelineKorey Sewell
speculative load/store pipelines can reenable this
2011-06-19inorder: fetchBuffer trackingKorey Sewell
calculate blocks in use for the fetch buffer to figure out how many total blocks are pending
2011-06-19inorder: redefine DynInst FP result typeKorey Sewell
Sharing the FP value w/the integer values was giving inconsistent results esp. when their is a 32-bit integer register matched w/a 64-bit float value
2011-06-19inorder: treat SE mode syscalls as a trapping instructionKorey Sewell
define a syscallContext to schedule the syscall and then use syscall() to actually perform the action