Age | Commit message (Collapse) | Author |
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extra : convert_revision : 17a3e16e849bee88892223f0c993b19c15daa554
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extra : convert_revision : bfc0ac8e1c8a5d01d9fa5203184bbf99c8361da3
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SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses
The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
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extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
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extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
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extra : convert_revision : e5d415b4bf79353ef3c9f4dc5af09ab4102c55fb
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extra : convert_revision : 4446d9544d58bdadbd24d8322bb63016a32aa2b8
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into multiple memory access.
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extra : convert_revision : 600f79f32ef30a6e1db951503bcfe8cd332858d1
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counted.
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extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
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extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
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extra : convert_revision : 9ef81afcfabd86c9c069204998c987344f03f33e
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It should be cleared prior to the call to recvRetry.
Add extra DPRINTF statement for clearer debugging output.
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extra : convert_revision : e2332754743f42d60e159ac89f6fb0fd8b7f57f8
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doesn't cause a false branch mispredict.
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extra : convert_revision : 2820597cc966cd7b128cef0dab48fe05089533d7
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extra : convert_revision : 3c480537bf38f74f0f1d72e75c70aa46ba91b759
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Lets CPU accesses to physical memory bypass Bus.
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extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
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extra : convert_revision : e6ef262bbbc5ad53498e55caac1897e6cc2a61e6
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Improve MRU checking for StaticInst, Bus, TLB
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extra : convert_revision : 9116b5655cd2986aeb4205438aad4a0f5a440006
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extra : convert_revision : ae7b3df573368c29a66d5b027ecad9ffb3a99104
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Also some touch up for ruflag.
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extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
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extra : convert_revision : 689e5b85c47bb2aaceb7eb38c2a24a2e5b69376c
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extra : convert_revision : 5fdd5a9595c3e5d6ce5f9e8c9af0a8e6c857551c
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extra : convert_revision : fe313718dba8236f3e9bceb49f8c5efccfc06a06
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extra : convert_revision : 444901221e9a0b991213fbcd555f2f5cca67e91b
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Ignore different values or rcx and r11 after a syscall until either the local or remote value changes. Also change the codes organization somewhat.
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extra : convert_revision : 2c1f69d4e55b443e68bfc7b43e8387b02cf0b6b5
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extra : convert_revision : 1d0b3afdd8254f5b2fb4bbff1fa4a0536f78bb06
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extra : convert_revision : af16bc685ea28e44b8120f16b72f60a21d68c1e2
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extra : convert_revision : 09610ad84afa605db2d0eab9945eb9809f297182
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extra : convert_revision : d00b7b09c7f19bc0e37b385ef7c124f69c0e917f
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People should never put pointers in DPRINTFs; it messes up
tracediffs. Plus these used the FullCPU trace flag, which
is not right.
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extra : convert_revision : 82ed56757da0ad947c165ba205b5f752c85c6667
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The correct order is unintuitively rax, rcx, rdx, rbx, etc, not rax, rbx, rcx, rdx.
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extra : convert_revision : 3abe6a723a6e30becfe34f8da707ea2ff5d4df77
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These need to be refined a little still and given parameters.
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extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
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extra : convert_revision : 367bf2431bf4f4eb7c4d5723816e5db6f7233aed
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extra : convert_revision : 688ba4d882cad2c96cf44c9e46999f74266e02ee
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extra : convert_revision : e06a950964286604274fba81dcca362d75847233
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Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg.
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extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
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creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
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extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
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extra : convert_revision : b41571535f3d1f78df3cb6e48c16de5c7549d87f
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extra : convert_revision : 1940a5d231b4f856cf69578f68ea98435824dbd8
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Atomic mode seems to work. Timing is closer but not there yet.
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extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
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Also make default 0, and make that mean run forever.
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extra : convert_revision : 3e60a52b1c5e334a9ef3d744cf7ee1d851ba4aa9
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src/cpu/simple/timing.cc:
Fix another SC problem.
src/mem/cache/cache_impl.hh:
Forgot to call makeTimingResponse() on uncached timing responses.
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extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209
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src/cpu/simple/timing.cc:
Fix swap/stq_c command bug.
src/mem/packet.cc:
Fix incorrect LoadLockedReq command response field.
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extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
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extra : convert_revision : ab78d9d1d88c3698edfd653d71c8882e1272b781
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(they function as adjectives not nouns)
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extra : convert_revision : 6506474ff3356ae8c80ed276c3608d8a4680bfdb
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now encoded in cmd field.
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extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : b1c954c187e3b3172a194396ba63808253121195
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extra : convert_revision : 2c0be7a8c0a54ba5b1b2b69468f788d20abc8452
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into vm1.(none):/home/stever/bk/newmem-cache2
src/base/traceflags.py:
Hand merge.
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extra : convert_revision : 9e7539eeab4220ed7a7237457a8f336f79216924
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src/cpu/memtest/memtest.cc:
Need to set packet source field so that response from cache
doesn't run into assertion failure when copying source to dest.
src/mem/packet.hh:
Copy source field when copying packets.
Assert that source is valid before copying it to dest
when turning packets around.
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extra : convert_revision : 09e3cfda424aa89fe170e21e955b295746832bf8
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : aa50af3094f5d459f75b514179b6e3ec5e0bf1df
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src/arch/mips/SConscript:
"mips import pt.1".
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extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
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