| Age | Commit message (Expand) | Author |
|---|
| 2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
| 2014-09-20 | mem: Rename Bus to XBar to better reflect its behaviour | Andreas Hansson |
| 2014-09-20 | cpu: Update DRAM traffic gen | Wendy Elsasser |
| 2014-09-20 | base: Clean up redundant string functions and use C++11 | Andreas Hansson |
| 2014-09-20 | cpu: Add ExecFlags debug flag | Mitch Hayenga |
| 2014-09-20 | cpu: use probes infrastructure to do simpoint profiling | Dam Sunwoo |
| 2014-09-19 | arch: Pass faults by const reference where possible | Andreas Hansson |
| 2014-09-19 | cpu: Use a deque in o3 rename instruction queue | Andreas Hansson |
| 2014-09-19 | misc: Use safe_cast when assumptions are made about return value | Andreas Hansson |
| 2014-09-12 | cpu: Fix memory access in Minor not setting parent Request flags | Andrew Bardsley |
| 2014-09-12 | style: Fix line continuation, especially in debug messages | Andrew Bardsley |
| 2014-09-12 | minor: Fix typo in DPRINTF for Minor branch prediction | Andreas Hansson |
| 2014-09-09 | cpu: Only iterate over possible threads on the o3 cpu | Mitch Hayenga |
| 2014-09-09 | misc: Fix a number of unitialised variables and members | Andreas Hansson |
| 2014-09-03 | base: Use the global Mersenne twister throughout | Andreas Hansson |
| 2014-05-13 | mem: Refactor assignment of Packet types | Curtis Dunham |
| 2014-09-03 | cpu: Fix o3 drain bug | Mitch Hayenga |
| 2014-04-29 | arm: use condition code registers for ARM ISA | Curtis Dunham |
| 2014-09-03 | cpu: fix bimodal predictor to use correct global history reg | Dam Sunwoo |
| 2014-09-03 | cpu: Fix cache blocked load behavior in o3 cpu | Mitch Hayenga |
| 2014-09-03 | cpu: Fix o3 quiesce fetch bug | Mitch Hayenga |
| 2014-09-03 | cpu: Fix SMT scheduling issue with the O3 cpu | Mitch Hayenga |
| 2014-09-03 | cpu: Fix incorrect speculative branch predictor behavior | Mitch Hayenga |
| 2014-09-03 | cpu: Add a fetch queue to the o3 cpu | Mitch Hayenga |
| 2014-09-03 | cpu: Fix o3 front-end pipeline interlock behavior | Mitch Hayenga |
| 2014-09-03 | cpu: Change writeback modeling for outstanding instructions | Mitch Hayenga |
| 2014-09-03 | arch, cpu: Factor out the ExecContext into a proper base class | Andreas Sandberg |
| 2014-09-01 | mem: change the namespace Message to ProtoMessage | Nilay Vaish |
| 2014-09-01 | ruby: eliminate type Time | Nilay Vaish |
| 2014-08-13 | scons: Build the branch predictor for all CPUs | Andreas Sandberg |
| 2014-08-13 | cpu: Don't forward declare RefCountingPtr | Andreas Sandberg |
| 2014-08-13 | cpu: Modernise the branch predictor (STL and C++11) | Andreas Hansson |
| 2014-08-10 | cpu: Ensure the traffic generator suppresses non-memory packets | Andreas Hansson |
| 2014-07-23 | cpu: `Minor' in-order CPU model | Andrew Bardsley |
| 2014-06-30 | cpu: implement a bi-mode branch predictor | Anthony Gutierrez |
| 2014-06-21 | o3: make dispatch LSQ full check more selective | Binh Pham |
| 2014-06-21 | o3: split load & store queue full cases in rename | Binh Pham |
| 2014-05-31 | style: eliminate equality tests with true and false | Steve Reinhardt |
| 2014-05-23 | cpu: o3: remove stat totalCommittedInsts | Nilay Vaish |
| 2014-05-09 | cpu: Useful getters for ActivityRecorder | Andrew Bardsley |
| 2014-05-09 | cpu: Add flag name printing to StaticInst | Andrew Bardsley |
| 2014-05-09 | cpu: Timebuf const accessors | Andrew Bardsley |
| 2014-05-09 | arch, arm: Preserve TLB bootUncacheability when switching CPUs | Geoffrey Blake |
| 2014-05-09 | cpu: add more instruction mix statistics | Curtis Dunham |
| 2014-05-09 | cpu, arm: Allow the specification of a socket field | Akash Bagdia |
| 2014-04-23 | cpu: Fix setTranslateLatency() bug for squashed instructions | Mitchell Hayenga |
| 2014-04-01 | cpu: Fix case where o3 lsq could print out uninitialized data | Mitch Hayenga |
| 2014-04-23 | cpu: Add O3 CPU width checks | Dam Sunwoo |
| 2014-04-19 | o3: Fix occupancy checks for SMT | Faissal Sleiman |
| 2014-04-09 | kvm, x86: Add initial support for multicore simulation | Andreas Sandberg |
