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Age
Commit message (
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Author
2011-02-12
inorder: utilize cached skeds in pipeline
Korey Sewell
2011-02-12
inorder: define iterator for resource schedules
Korey Sewell
2011-02-12
inorder: stage scheduler for front/back end schedule creation
Korey Sewell
2011-02-12
inorder: cache instruction schedules
Korey Sewell
2011-02-12
inorder: comments for resource sked class
Korey Sewell
2011-02-12
inorder: remove unused file
Korey Sewell
2011-02-11
O3: Fix pipeline restart when a table walk completes in the fetch stage.
Giacomo Gabrielli
2011-02-11
SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk o...
Ali Saidi
2011-02-11
O3: Enhance data address translation by supporting hardware page table walkers.
Giacomo Gabrielli
2011-02-06
m5: added work completed monitoring support
Brad Beckmann
2011-02-06
TimingSimpleCPU: split data sender state fix
Joel Hestness
2011-02-06
mcpat: Adds McPAT performance counters
Joel Hestness
2011-02-04
inorder: fault handling
Korey Sewell
2011-02-04
inorder: pcstate and delay slots bug
Korey Sewell
2011-02-04
inorder: add a fetch buffer to fetch unit
Korey Sewell
2011-02-04
inorder: overload find-req fn
Korey Sewell
2011-02-04
inorder: implement separate fetch unit
Korey Sewell
2011-02-04
inorder: cache port blocking
Korey Sewell
2011-02-04
inorder: stage width as a python parameter
Korey Sewell
2011-02-04
inorder: multi-issue branch resolution
Korey Sewell
2011-02-04
inorder: pipe. stage inst. buffering
Korey Sewell
2011-02-04
inorder: change skidBuffer to list instead of queue
Korey Sewell
2011-02-04
inorder: activity tracking bug
Korey Sewell
2011-02-03
Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.
Gabe Black
2011-02-03
Config: Keep track of uncached and cached ports separately.
Gabe Black
2011-02-02
O3: Fix a style bug in O3.
Gabe Black
2011-02-01
X86: Add L1 caches for the TLB walkers.
Gabe Black
2011-01-18
O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.
Matt Horsnell
2011-01-18
O3: Don't test misprediction on load instructions until executed.
Matt Horsnell
2011-01-18
O3: Keep around the last committed instruction and use for squashing.
Ali Saidi
2011-01-18
O3: Don't try to scoreboard misc registers.
Ali Saidi
2011-01-18
O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.
Matt Horsnell
2011-01-18
O3: Fix mispredicts from non control instructions.
Matt Horsnell
2011-01-18
O3: Fixes the way prefetches are handled inside the iew unit.
Matt Horsnell
2011-01-18
O3: Support timing translations for O3 CPU fetch.
Ali Saidi
2011-01-18
ARM: Add support for moving predicated false dest operands from sources.
Ali Saidi
2011-01-18
O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.
Min Kyu Jeong
2011-01-12
inorder: fix RUBY_FS build
Korey Sewell
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2011-01-07
inorder: replace schedEvent() code with reschedule().
Steve Reinhardt
2011-01-07
inorder: get rid of references to mainEventQueue.
Steve Reinhardt
2011-01-03
Move sched_list.hh and timebuf.hh from src/base to src/cpu.
Steve Reinhardt
2011-01-03
Make commenting on close namespace brackets consistent.
Steve Reinhardt
2010-12-22
This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh f...
Nilay Vaish
2010-12-21
memtest: delete some crufty dead code
Steve Reinhardt
2010-12-20
Style: Replace some tabs with spaces.
Gabe Black
2010-12-07
O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).
Ali Saidi
2010-12-07
O3: Support squashing all state after special instruction
Ali Saidi
2010-12-07
O3: Make all instructions that write a misc. register not perform the write u...
Giacomo Gabrielli
2010-12-07
O3: Support SWAP and predicated loads/store in ARM.
Min Kyu Jeong
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