summaryrefslogtreecommitdiff
path: root/src/cpu
AgeCommit message (Expand)Author
2013-05-30cpu: Prune the stale TraceCPUAndreas Hansson
2013-05-30cpu: Check that minimum TrafficGen period is less than max periodSascha Bischoff
2013-05-30cpu: Fix bug when reading in TrafficGen state transitionsSascha Bischoff
2013-05-30cpu: Add request elasticity to the traffic generatorAndreas Hansson
2013-05-30cpu: Block traffic generator when requests have to retryAndreas Hansson
2013-05-30cpu: Move traffic generator sending out of generator statesAndreas Hansson
2013-05-30cpu: Fold together the StateGraph and the TrafficGenAndreas Hansson
2013-05-30cpu: Make hash struct instead of class to please clangAndreas Hansson
2013-05-14cpu: remove local/globalHistoryBits params from branch predAnthony Gutierrez
2013-05-14kvm: Add support for disabling coalesced MMIOAndreas Sandberg
2013-05-14kvm: Dump state before panic in KVM exit handlersAndreas Sandberg
2013-05-14kvm: Fix the memory interface used by KVMAndreas Sandberg
2013-05-02kvm: Add a stat counting number of instructions executedAndreas Sandberg
2013-05-02kvm: Add checkpoint debug printAndreas Sandberg
2013-05-02kvm: Make MMIO requests uncacheableAndreas Sandberg
2013-04-23cpu: Fix TraceGen flag initalisationAndreas Hansson
2013-04-22cpu: Use request flags in trace playbackAndreas Hansson
2013-04-22cpu: Make the generators usable outside the TrafficGen moduleAndreas Hansson
2013-04-22kvm: Add support for pseudo-ops on ARMAndreas Sandberg
2013-04-22kvm: Add support for state dumping on ARMAndreas Sandberg
2013-04-22kvm: Add basic support for ARMAndreas Sandberg
2013-04-22kvm: Add experimental support for a perf-based execution timerAndreas Sandberg
2013-04-22kvm: Avoid synchronizing the TC on every KVM exitAndreas Sandberg
2013-04-22kvm: Basic support for hardware virtualized CPUsAndreas Sandberg
2013-04-22cpu: Let python scripts obtain the number of instructions executedTimothy M. Jones
2013-04-22arm: Enable support for triggering a sim panic on kernel panicsAndreas Sandberg
2013-04-22sim: separate nextCycle() and clockEdge() in clockedObjectsDam Sunwoo
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-04-22cpu: fix a switching issue with the o3 cpu.Ali Saidi
2013-03-29o3cpu: commit: changes interrupt handlingNilay Vaish
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-03-20cpu: Avoid including inorder TLBUnit to avoid gcc LTO bugAndreas Hansson
2013-03-12cpu: Fix state transition bug in the traffic generatorAndreas Sandberg
2013-03-04cpu: fix a switching issue with the o3 cpu.Ali Saidi
2013-02-19scons: Fix warnings issued by clang 3.2svn (XCode 4.6)Andreas Hansson
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
2013-02-15cpu: Document exec trace flagsAndreas Sandberg
2013-02-15cpu: Avoid duplicate entries in tracking structures for writes to misc regsGeoffrey Blake
2013-02-15cpu: Fix rename mis-handling serializing instructions when resource constrainedGeoffrey Blake
2013-02-15o3: fix tick used for renaming and issue with range selectionMatt Horsnell
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-02-15cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchyAndreas Sandberg
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-02-15cpu: include set in o3/commit_impl.Ali Saidi
2013-02-15cpu: fix case with o3 cpu blocking and unblocking decode in cycleAli Saidi
2013-02-15cpu: Fix a livelock in the o3 cpu.Ali Saidi
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 05:29:47 +0000