| Age | Commit message (Expand) | Author |
|---|
| 2015-10-06 | sim: add ExecMacro to Exec* compound debug flags | Steve Reinhardt |
| 2015-09-30 | base: remove Trace::enabled flag | Curtis Dunham |
| 2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
| 2015-09-30 | isa,cpu: Add support for FS SMT Interrupts | Mitch Hayenga |
| 2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
| 2015-09-30 | config,cpu: Add SMT support to Atomic and Timing CPUs | Mitch Hayenga |
| 2015-09-30 | cpu: Change thread assignments for heterogenous SMT | Mitch Hayenga |
| 2015-09-15 | cpu: pred: Local Predictor Reset in Tournament Predictor | Andrew Lukefahr |
| 2015-09-15 | cpu, o3: consider split requests for LSQ checksnoop operations | Hongil Yoon |
| 2015-08-29 | ruby: eliminate type uint64 and int64 | Nilay Vaish |
| 2015-08-21 | mem: Reflect that packet address and size are always valid | Andreas Hansson |
| 2015-08-21 | cpu: Move invldPid constant from Request to BaseCPU | Andreas Hansson |
| 2015-08-19 | ruby: reverts to changeset: bf82f1f7b040 | Nilay Vaish |
| 2015-08-14 | ruby: eliminate type uint64 and int64 | Nilay Vaish |
| 2015-08-14 | ruby: replace Address by Addr | Nilay Vaish |
| 2015-08-11 | ruby: drop some redundant includes | Nilay Vaish |
| 2015-08-07 | base: Declare a type for context IDs | Andreas Sandberg |
| 2015-07-20 | cpu: Fixed a bug on where to fetch the next instruction from | David Hashe |
| 2015-07-31 | cpu: Update debug message from Fetch1 isDrained() in Minor | Andreas Sandberg |
| 2015-07-31 | cpu: Fix Minor drain issues when switched out | Andreas Sandberg |
| 2015-07-30 | cpu: Only activate thread 0 in Minor if the CPU is active | Andreas Sandberg |
| 2015-07-30 | cpu: Fix drain issues in the Minor CPU | Andreas Sandberg |
| 2015-07-30 | cpu: Fix issue identified by UBSan | Andreas Hansson |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-07-26 | cpu: o3: slight correction to identation in rename_impl.hh | Nilay Vaish |
| 2015-07-10 | ruby: replace global g_abs_controls with per-RubySystem var | Brandon Potter |
| 2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
| 2015-07-07 | sim: Make the drain state a global typed enum | Andreas Sandberg |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-07-04 | o3: correct the number of cc registers in rename map | Nilay Vaish |
| 2015-06-01 | kvm, arm: Add support for aarch64 | Andreas Sandberg |
| 2015-06-01 | kvm, arm, dev: Add an in-kernel GIC implementation | Andreas Sandberg |
| 2015-06-01 | kvm: Handle inst events at the current instruction count | Andreas Sandberg |
| 2015-06-01 | kvm, arm: Move ARM-specific files to arch/arm/kvm/ | Andreas Sandberg |
| 2015-05-26 | cpu: Fix a bug in counting issued instructions in MinorCPU | Andrew Bardsley |
| 2015-05-23 | kvm: Fix dumping code for large registers | Andreas Sandberg |
| 2015-05-23 | kvm, x86: Guard x86-specific APIs in KvmVM | Andreas Sandberg |
| 2015-05-15 | misc: Appease gcc 5.1 | Andreas Hansson |
| 2015-05-05 | mem, cpu: Add a separate flag for strictly ordered memory | Andreas Sandberg |
| 2015-05-05 | mem: Snoop into caches on uncacheable accesses | Andreas Hansson |
| 2015-05-05 | cpu: Work around gcc 4.9 issues with Num_OpClasses | Andreas Hansson |
| 2015-04-29 | cpu: o3: replace issueLatency with bool pipelined | Nilay Vaish |
| 2015-04-29 | cpu: o3: single cycle default div microop latency on x86 | Nilay Vaish |
| 2015-04-22 | cpu: remove conditional check (count > 0) on o3 IQ squashes | Brandon Potter |
| 2015-04-20 | cpu: Remove the InOrderCPU from the tree | Andreas Hansson |
| 2015-04-14 | config, cpu: fix progress interval for switched CPUs | Malek Musleh |
| 2015-04-13 | cpu: re-organizes the branch predictor structure. | Dibakar Gope |
| 2015-04-03 | cpu: fix system total instructions accounting | Nikos Nikoleris |
| 2015-03-26 | cpu: Fix InstPBTrace inheritance | Andreas Hansson |
