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2018-03-27cpu: Remove ExtMachInst typedefs from the O3 CPU model.Gabe Black
These typedefs aren't used, and they expose ISA specific types outside the ISA implementations. Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34 Reviewed-on: https://gem5-review.googlesource.com/9404 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-27arch: cpu: Make the ExtMachInst type a template argument in InstMap.Gabe Black
This doesn't completely hide the ISA specific ExtMachInst type inside the ISAs since it still gets applied in arch/generic, but it at least pulls it into the arch directory. Change-Id: Ic2188d59696530d7ecafdff0785d71867182701d Reviewed-on: https://gem5-review.googlesource.com/9403 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-27cpu: Stop extracting inst_flags from the machInst.Gabe Black
The instruction representation is already encoded in the trace protobuf, so there's no reason to encode a part of it again. This is especially true since this supposedly generic code is extracting the first 8 bits of the machInst, a totally arbitrary set of bits for most ISAs. If certain bits within a machine instruction are actually relevant, the consumer of the trace should be able to interpret the instruction bytes which are already there and extract the same bits within the context of whatever ISA they're appropriate for. Change-Id: Idaebe6a110d7d4812c3d7c434582d5a9470bcec1 Reviewed-on: https://gem5-review.googlesource.com/9401 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26cpu: Use the new asBytes function in the protobuf inst tracer.Gabe Black
Use this function to get the binary representation of the instruction rather than referencing the ExtMachInst typed machInst member of the StaticInst directly. ExtMachInst is an ISA specific type and can't always be straightforwardly squished into a 32 bit integer. Change-Id: Ic1f74d6d86eb779016677ae45c022939ce3e2b9f Reviewed-on: https://gem5-review.googlesource.com/7563 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26arch: Add a virtual asBytes function to the StaticInst class.Gabe Black
This function takes a pointer to a buffer and the current size of the buffer as a pass by reference argument. If the size of the buffer is sufficient, the function stores a binary representation of itself (generally the ISA defined instruction encoding) in the buffer, and sets the size argument to how much space it used. This could be used by ISAs which have two instruction sizes (ARM and thumb, for example). If the buffer size isn't sufficient, then the size parameter should be set to what size is required, and then the function should return without modifying the buffer. The buffer itself should be aligned to the same standard as memory returned by new, specifically "The pointer returned shall be suitably aligned so that it can be converted to a pointer of any complete object type and then used to access the object or array in the storage allocated...". This will avoid having to memcpy buffers to avoid unaligned accesses. To standardize the representation of the data, it should be stored in the buffer as little endian. Since most hosts (including ARM and x86 hosts) will be little endian, this will almost always be a no-op. Change-Id: I2f31aa0b4f9c0126b44f47a881c2901243279bd6 Reviewed-on: https://gem5-review.googlesource.com/7562 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-23ruby: Make sure addresses print in hexJason Lowe-Power
Added fix in the invalid transition panic and various places in ruby random tester. Change-Id: I879264da58369faf7de49d1a28b2da1cb935ef0a Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8941 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
Starting with version 3, scons imposes using the print function instead of the print statement in code it processes. To get things building again, this change moves all python code within gem5 to use the function version. Another change by another author separately made this same change to the site_tools and site_init.py files. Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0 Reviewed-on: https://gem5-review.googlesource.com/8761 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-02-20cpu-o3: Don't add non-speculative mem barriers to the IQ twiceAndreas Sandberg
There are cases where the IEW adds a non-speculative instruction to the IQ twice. This can happen if an instruction is flagged as IsMemBarrier and IsNonSpeculative. Avoid adding non-speculative instructions in the IEW to the IQ by checking if it has been added already. Change-Id: Ifcff676a451b57b2406ce00ed8dae19ed399515f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Javier Setoain <javier.setoain@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8374 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-02-05cpu: MinorCPU handling IsSquashAfter flagGiacomo Travaglini
MinorCPU was not handling IsSquashAfter flagged instructions. The behaviour was to force a branch (hence enforcing refetching) for SerializeAfter instructions only. This has now been extended to SquashAfter in order to correctly support ISB barrier instruction behaviour. Change-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5702 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arm: DT autogeneration - Generate cpus nodeGlenn Bergmans
Equips cpu models with a method to generate the cpu node. Note: even though official documentation requires that CPU ids start counting from 0 in every cluster, GEM5 requires a globally unique cpu_id. Change-Id: Ida3e17af3124a68ef7dbf2449cd034dfc3ec39df Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5963 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-12sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().Xiaoyu Ma
Before this CL, the addTwoLevelCacheHierarchy() function uses the default L2XBar class as the interconnect between CPU L1 caches and L2. This CL allows passing a user-defined bus to overwrite the default L2XBar by adding an optional argument to the function. Change-Id: I917657272fd4924ee0bed882a226851afba26847 Reviewed-on: https://gem5-review.googlesource.com/7364 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-11cpu: Make the CPU's TLB parameter a BaseTLB.Gabe Black
This is instead of the architecture specific version. Change-Id: I906ec16eee1f65f0e9b9c24b401430f9ea01637b Reviewed-on: https://gem5-review.googlesource.com/7349 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-10style: change C/C++ source permissions to noexecBKP
Several files in the repository were tracked with execute permissions even though the files are just normal C/C++ files (and the one .isa). Change-Id: I976b096acab4a1fc74c5699ef1f9b222c1e635c2 Reviewed-on: https://gem5-review.googlesource.com/7241 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-10alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.Gabe Black
This constant is, first, a #define, and second only used in one place. In that one place, it appears that the code it guards is no longer necessary in general. It was originally written to avoid refetching a block of data that you're still in, even if you've moved slightly farther in it because you're skipping the next instruction due to an annulled branch delay slot. In reality however, in SPARC, the one ISA I'm aware of which has this sort of branching behavior, the PC state object will correctly determine that no branch is happening in these cases. Code lower down in the loop will then recompute where fetching should continue based on the next PC, automatically skipping the annulled branch slot without misinterpretting the gap as a branch. This change therefore also removes this block of code. Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c Reviewed-on: https://gem5-review.googlesource.com/6821 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-09cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults.Gabe Black
When a fault happens in fetch in O3, a dummy inst is created to carry the fault through the pipeline to commit, but conceptually there isn't actually any instruction since we failed to fetch one. This change marks the dummy instruction as NotAnInst, and when any such instruction gets to commit, the fault object associated with it is invoked and passed a null static inst pointer instead of a pointer to the dummy inst. Change-Id: I18d993083406deb625402e06af4ba0d4772ca5a3 Reviewed-on: https://gem5-review.googlesource.com/7124 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-09cpu: Add a NotAnInst flag to the BaseDynInst class.Gabe Black
This flag means that the instruction isn't an actual instruction, it's just a placeholder to carry a fault down a pipeline, for instance. Change-Id: I1cc12b068662dbd3d3b089c9941a07b6e88b57e3 Reviewed-on: https://gem5-review.googlesource.com/7123 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-09cpu, power: Get rid of the remnants of the EA computation insts.Gabe Black
Get rid of some remnants of a system which was intended to separate address computation into its own instruction object. Change-Id: I23f9ffd70fcb89a8ea5bbb934507fb00da9a0b7f Reviewed-on: https://gem5-review.googlesource.com/7122 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
CPUs have historically instantiated the architecture specific version of the TLBs to avoid a virtual function call, making them a little bit more dependent on what the current ISA is. Some simple performance measurement, the x86 twolf regression on the atomic CPU, shows that there isn't actually any performance benefit, and if anything the simulator goes slightly faster (although still within margin of error) when the TLB functions are virtual. This change switches everything outside of the architectures themselves to use the generic BaseTLB type, and then inside the ISA for them to cast that to their architecture specific type to call into architecture specific interfaces. The ARM TLB needed the most adjustment since it was using non-standard translation function signatures. Specifically, they all took an extra "type" parameter which defaulted to normal, and translateTiming returned a Fault. translateTiming actually doesn't need to return a Fault because everywhere that consumed it just stored it into a structure which it then deleted(?), and the fault is stored in the Translation object when the translation is done. A little more work is needed to fully obviate the arch/tlb.hh header, so the TheISA::TLB type is still visible outside of the ISAs. Specifically, the TlbEntry type is used in the generic PageTable which lives in src/mem. Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575 Reviewed-on: https://gem5-review.googlesource.com/6921 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-22cpu: Use the generic nop static inst instead of decoding the arch version.Gabe Black
This removes a dependence on the ISA. Change-Id: I01013bc70558f0831327213912bcac11258066a6 Reviewed-on: https://gem5-review.googlesource.com/6824 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-22cpu: Add a pointer to a generic Nop StaticInst.Gabe Black
This can be used whenever generic code needs a filler instruction that doesn't do anything. Change-Id: Ib245d3e880a951e229eb315a09ecc7c47e6ae00f Reviewed-on: https://gem5-review.googlesource.com/6823 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-20cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.Gabe Black
Change-Id: I868021a01eb3e7902a4d64283bdfaa93c6d9f964 Reviewed-on: https://gem5-review.googlesource.com/6822 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-19cpu-tester: Added ExitGen to TrafficGenRiken Gohil
Added the ExitGen to the TrafficGenerator which allows an EXIT state to be added to the TrafficGen configuration file. Entering this state will cause the simulation to exit immediately. Please note that if multiple TrafficGen instances have an EXIT state, the first of these to be encountered will cause the simulation to terminate. Change-Id: Ieea51f05ffb780771f007787a2b119f79143d0c1 Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5723 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-19cpu-tester: Refactoring traffic generators into separate files.Riken Gohil
Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
GCC 7.2 is much stricter than previous GCC versions. The following changes are needed: * There is now a warning if there is an implicit fallthrough between two case statments. C++17 adds the [[fallthrough]]; declaration. However, to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH. M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and if that doesn't exist, it defaults to nothing (no older compilers generate warnings). * The above resulted in a couple of bugs that were found. This is noted in the review request on gerrit. * throw() for dynamic exception specification is deprecated * There were a couple of new uninitialized variable warnings * Can no longer perform bitwise operations on a bool. * Must now include <functional> for std::function * Compiler bug for void* lambda. Changed to auto as work around. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878 Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5802 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
Replace them with std::array<>s. Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34 Reviewed-on: https://gem5-review.googlesource.com/6602 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
Neither of these were used, particularly memAccInst. Change-Id: I4ac9e44cf624e5de42519d586d7b699f08a2cdfc Reviewed-on: https://gem5-review.googlesource.com/6601 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-08x86,misc: add additional info on faulting X86 instruction, fetched PCMatt Sinclair
Print faulting instruction for unmapped address panic in faults.cc and print extra info about corresponding fetched PC in base.cc. Change-Id: Id9e15d3e88df2ad6b809fb3cf9f6ae97e9e97e0f Reviewed-on: https://gem5-review.googlesource.com/6461 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-05cpu: Add support for CMOs in the cpu modelsNikos Nikoleris
Cache maintenance operations go through the write channel of the cpu. This changes makes sure that the cpu does not try to fill in the packet with data. Change-Id: Ic83205bb1cda7967636d88f15adcb475eb38d158 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5055 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.). Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-29cpu: Don't override ISA if provided by userAndreas Sandberg
The BaseCPU.createThreads() method currently overrides the BaseCPU.isa parameter. This is sometimes undesirable. Change the behavior so that the default value for the isa parameter is the empty list and teach createThreads() to only override the ISA if none has been specified. Change-Id: I2ac5535e55fc57057e294d3c6a93088b33bf7b84 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6121 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-29cpu-minor: Add missing instruction statsDavid Guillen Fandos
Change-Id: I811b552989caf3601ac65a128dbee6b7bb405d7f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Updated to use IsVector instruction flag. ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5732 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-28cpu-o3: Add missing vector stat initializersAndreas Sandberg
All of the O3 vector stats added by 'arch: ISA parser additions of vector registers' are currently missing their stat initializers. Add the missing stat initialization to InstructionQueue::regStats. Change-Id: Idc4b8e2824120a2542d8a604340a1b41bde6aa28 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6101 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-11-21cpu, cpu, sim: move Cycle probe updateJose Marinho
Move the code responsible for performing the actual probe point notify into BaseCPU. Use BaseCPU activateContext and suspendContext to keep track of sleep cycles. Create a probe point (ppActiveCycles) that does not count cycles where the processor was asleep. Rename ppCycles to ppAllCycles to reflect its nature. Change-Id: I1907ddd07d0ff9f2ef22cc9f61f5f46c630c9d66 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5762 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-21cpu-o3: Prevent cpu from suspending if it is already drainingNikos Nikoleris
Suspending the current thread context while draining due to a quiesce pseudo instruction (for example a wfi instruction) could deadlock the cpu and prevent it from successfully draining. This change ensures that the cpu is not draining before suspending the thread context. Change-Id: I7c019847f5a870d4bc9ce2b19936bc3dc45e5fd7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5881 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-20cpu: Make automatic transition to OFF optionalJose Marinho
Add the power_gating_on_idle option to control whether a core automatically enters the power gated state. The default behaviour is to transition to clock gated when idle, but not to power gated. When this option is set to true, the core automatically transitions to the power gated state after a configurable latency. Change-Id: Ida98c7fc532de4140d0e511c25613769b47b3702 Reviewed-on: https://gem5-review.googlesource.com/5741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-20pwr: Adds logic to enter power gating for the cpu modelAnouk Van Laer
If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-14cpu, probe: Fix elastic trace register dependencyRadhika Jagtap
Change-Id: I017852eac183fac3f914fdb96d7e72a56ea9d682 Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5121 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-19cpu-o3: Add M5_VAR_USED to variableJason Lowe-Power
Fixes compile error for gem5.fast on CLANG due to unused variable. Change-Id: Iabe777a27d75ee8bfa7b214fff577aed3c7582c7 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4980 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-10-13cpu-o3: Check predication before the SQ size for a debug printNikos Nikoleris
The size of the store entry in the LSQ is used to indicate a fault in the execution of the store. At the same time, a store that is predicated false will also have 0 size in the corresponding store queue entry. This changeset ensures that we check if the store was predicated false before checking the size field. This way we avoid printing stores as faulting when they are only predicated false. Change-Id: Ie07982197bd73d7b44d26a3257d54ecb103a952a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4821 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-13cpu-o3: Avoid early checker verification for store conditionalsNikos Nikoleris
The O3CPU allows stores to commit before they are completed and as soon as they enter the store queue. This is the reason why stores are verified by the the checker CPU, separately, once they complete and after they are sent to the memory. Store conditionals, on the other hand, have an additional writeback stage in the pipeline as they return their result to a register, similarly to loads. This is the reason why they do not commit before they receive a response from the memory. This allows store conditionals to be verified by the checker CPU as soon as they commit in the same way as all other non-store insturctions. At the same time, the presense of a checker CPU should not require changes to way we handle instructions. This change removes explicit calls to: * incorrectly set the extra data of the request to 0 (a subsequent call to completeAcc already does this without making any ISA assumptions about the return value of the failed store conditional) * complete failing store conditionals Change-Id: If21d70b21caa55b35e9fdcc50f254c590465d3c3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4820 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-11stats: Get rid of some kernel stats related cruft.Gabe Black
The kernel stat mechanism should really be refactored and moved somewhere else, but in the mean time there's some old cruft that can be cleared away. Change-Id: I21e725de590dda0d20bf3bc675bbe976c7b1bd86 Reviewed-on: https://gem5-review.googlesource.com/4600 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-06cpu: Fix bi-mode branch predictor thresholdsRico Amslinger
When different sizes were set for the choice and global saturation counter (e.g. ex5_big), the threshold calculation used the wrong size. Thus the branch predictor always predicted "not taken" for choice > global. Change-Id: I076549ff1482e2280cef24a0d16b7bb2122d4110 Reviewed-on: https://gem5-review.googlesource.com/4560 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-09-01cpu-minor: Fix for addr range coverage calculationPau Cabre
Coverage was wrongly set to PartialAddrRangeCoverage in the case of disjoint adjacent ranges Change-Id: I29aaf5145e6cdcf5f0b8f4e009d57ee57bd4c944 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/4640 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-30cpu-o3: fix data pkt initialization for split loadMatthias Hille
When a split load hits a memory region where IPRs are mapped, the Writebackevent which is scheduled for that was carrying a data packet that was not correctly initialized which caused an assertion to fire when the Writeback event is processed. Change-Id: I71a4e291f0086f7468d7e8124a0a8f098088972f Signed-off-by: Matthias Hille <matthiashille8@gmail.com> Reported-by: Matthias Hille <matthiashille8@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/4620 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-01kvm: Add a helper method to access device event queuesAndreas Sandberg
The VM's event queue is normally used for devices in multi-core KVM mode. Add a helper method, BaseKvmCPU::deviceEventQueue(), to access this queue. This makes the intention of code migrating to device event queues clearer. Change-Id: Ifb10f553a6d7445c8d562f658cf9d0b1f4c577ff Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4287 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01cpu, kvm: Fix deadlock issue when resuming a drained systemAndreas Sandberg
The KVM CPU sometimes needs to access devices when drain() is called. This typically happens on ARM when synchronizing devices that use the system register interface. When called from drain(), the event queue isn't locked since drain is called from the outside when the simulator isn't servicing any events. In such cases, performing a migration to the device's queue will unlock a mutex that isn't locked. This typically results in a deadlock when resuming the system since the lock will be in an undefined state. Change-Id: Ibdcc2e034e916a929124f297e72aae306cf66728 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4286 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-19cpu: Add missing rename of vector registers in the O3 CPURekai Gonzalez-Alberquilla
The introduction of a new vector register class broke rename in the O3 CPU due to an unhandled register class in DefaultRename<Impl>::renameSrcRegs(). This patch fixes adds the necessary handling to avoid a panic when the vector register file is used. Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4140 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-17cpu,o3: Fixed checkpointing bug occuring in the o3 CPUAnouk Van Laer
Checkpointing a system with out-of-order CPUs might get stuck if one of the CPUs has been put to sleep. The quiesce instruction cannot get drained hence checkpointing never finishes. This commit resolves that by activating all suspended thread contexts when draining the system. Change-Id: I817ab1672b4ead777bd8e12a0445829481c46fdc Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3970 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-12testers: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: I897b6162a827216b7bad74d955c0e50e06a5a3ec Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3926 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-12kvm, mem: Refactor some Event subclasses into lambdasSean Wilson
Change-Id: Ifafdcf4692d58a17f90e66ff8de8fa3e146c34bb Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3924 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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