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2007-10-02Merge with head.Gabe Black
--HG-- extra : convert_revision : 1aa0e4569a7c10e6a395c2c951ac29275b5bcf59
2007-10-02Predecoder: Clear out predecoder state on an ITLB fault.Gabe Black
--HG-- extra : convert_revision : 68f8ff778dbd28ade5070edf5a7d662e7bf0045a
2007-10-02CPU: Make the cpuid parameter get set in SE mode as well.Gabe Black
--HG-- extra : convert_revision : bc47206acb683ebaaa31f57af79b4b8db64e4d31
2007-10-02CPU: Make the cpus check the pc event queues in SE mode.Gabe Black
--HG-- extra : convert_revision : 9dc4ea136c3c3f87a73d55e91bc4aae4eba70464
2007-10-02CPU: Make sure the system parameter gets set in the cpu builders. Other ↵Gabe Black
parameters need to be fixed as well. --HG-- extra : convert_revision : 0401970a79855ee0a96eb29305346ce07b5c98ea
2007-10-01CPU: fix sparc_fs booting with SimpleTimingCPU.Ali Saidi
--HG-- extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885
2007-09-28Update stats for quiesced cyclesAli Saidi
--HG-- extra : convert_revision : 703ba58f156c9f2677b020f05d36bc1e3ae0b9e5
2007-09-28Rename cycles() function to ticks()Ali Saidi
--HG-- extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
2007-09-28Update statistics to use cycles properly instead of ticksAli Saidi
--HG-- extra : convert_revision : 62911280b631ef24720f9ce701d1c19a9b8a9784
2007-09-25Merge with head.Gabe Black
--HG-- extra : convert_revision : f331b9cbd82086d63d4f35e18f9e08466c016225
2007-09-25SPARC: Fix a stupid mistake which was breaking the SPARC regressions.Gabe Black
--HG-- extra : convert_revision : 34a11df0d467ea249211dd3aba86bc8d2aea45de
2007-09-24X86: Get X86_FS to compile.Gabe Black
--HG-- extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01
2007-09-19X86: Put in the foundation for x87 stack based fp registers.Gabe Black
--HG-- extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
2007-09-04X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and ↵Gabe Black
actually compare xmm. --HG-- extra : convert_revision : 02c6641200edb133c9bc11f1fdf3c1a0b1c87e77
2007-08-31X86: Get x86 to compile again after the simobject constructor change.Gabe Black
--HG-- extra : convert_revision : 17a3e16e849bee88892223f0c993b19c15daa554
2007-08-30Fix miscellaneous small typos.Miles Kaufmann
--HG-- extra : convert_revision : bfc0ac8e1c8a5d01d9fa5203184bbf99c8361da3
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-26Merge with headGabe Black
--HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
2007-08-26O3 CPU: Remove alignment check from dynamic instruction read/write functions.Gabe Black
--HG-- extra : convert_revision : e5d415b4bf79353ef3c9f4dc5af09ab4102c55fb
2007-08-26Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.Gabe Black
--HG-- extra : convert_revision : 4446d9544d58bdadbd24d8322bb63016a32aa2b8
2007-08-26Simple CPU: Added code that will split requests that cross block boundaries ↵Gabe Black
into multiple memory access. --HG-- extra : convert_revision : 600f79f32ef30a6e1db951503bcfe8cd332858d1
2007-08-26Simple CPU: Make sure only instructions which complete without faulting are ↵Gabe Black
counted. --HG-- extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
2007-08-21Merge with head.Gabe Black
--HG-- extra : convert_revision : 9ef81afcfabd86c9c069204998c987344f03f33e
2007-08-21o3: Fix for retry ID bug.Kevin Lim
It should be cleared prior to the call to recvRetry. Add extra DPRINTF statement for clearer debugging output. --HG-- extra : convert_revision : e2332754743f42d60e159ac89f6fb0fd8b7f57f8
2007-08-13O3: Set up the predicted npc and nnpc for a fault carrying noop so that it ↵Gabe Black
doesn't cause a false branch mispredict. --HG-- extra : convert_revision : 2820597cc966cd7b128cef0dab48fe05089533d7
2007-08-13Move the "translate" member functions back into the base o3 class.Gabe Black
--HG-- extra : convert_revision : 3c480537bf38f74f0f1d72e75c70aa46ba91b759
2007-08-08Added fastmem option.Vincentius Robby
Lets CPU accesses to physical memory bypass Bus. --HG-- extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
2007-08-08Port, StaticInst: Revert unnecessary changes.Vincentius Robby
--HG-- extra : convert_revision : e6ef262bbbc5ad53498e55caac1897e6cc2a61e6
2007-08-08alpha: Make the TLB cache to actually work.Vincentius Robby
Improve MRU checking for StaticInst, Bus, TLB --HG-- extra : convert_revision : 9116b5655cd2986aeb4205438aad4a0f5a440006
2007-08-07Merge with head.Gabe Black
--HG-- extra : convert_revision : ae7b3df573368c29a66d5b027ecad9ffb3a99104
2007-08-07X86: Make a microcode branch microop.Gabe Black
Also some touch up for ruflag. --HG-- extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
2007-08-04switching: turn on profiling after a switch if there's an eventNathan Binkert
--HG-- extra : convert_revision : 689e5b85c47bb2aaceb7eb38c2a24a2e5b69376c
2007-08-04SimpleCPU: Add some DPRINTFsNathan Binkert
--HG-- extra : convert_revision : 5fdd5a9595c3e5d6ce5f9e8c9af0a8e6c857551c
2007-08-04StaticInst: Fix decode cache initialization. Cache functionality was negated.Vincentius Robby
--HG-- extra : convert_revision : fe313718dba8236f3e9bceb49f8c5efccfc06a06
2007-08-01Merge with head.Gabe Black
--HG-- extra : convert_revision : 444901221e9a0b991213fbcd555f2f5cca67e91b
2007-08-01X86: Reorganize the native tracing code.Gabe Black
Ignore different values or rcx and r11 after a syscall until either the local or remote value changes. Also change the codes organization somewhat. --HG-- extra : convert_revision : 2c1f69d4e55b443e68bfc7b43e8387b02cf0b6b5
2007-07-31Add a flag to indicate an instruction triggers a syscall in SE mode.Gabe Black
--HG-- extra : convert_revision : 1d0b3afdd8254f5b2fb4bbff1fa4a0536f78bb06
2007-07-31Merge from head.Steve Reinhardt
--HG-- extra : convert_revision : af16bc685ea28e44b8120f16b72f60a21d68c1e2
2007-07-30Fix problem with tracer not being initialized.Gabe Black
--HG-- extra : convert_revision : 09610ad84afa605db2d0eab9945eb9809f297182
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
--HG-- extra : convert_revision : d00b7b09c7f19bc0e37b385ef7c124f69c0e917f
2007-07-29BsaeCPU: Get rid of some bad DPRINTFs.Steve Reinhardt
People should never put pointers in DPRINTFs; it messes up tracediffs. Plus these used the FullCPU trace flag, which is not right. --HG-- extra : convert_revision : 82ed56757da0ad947c165ba205b5f752c85c6667
2007-07-29X86: Fix register ordering.Gabe Black
The correct order is unintuitively rax, rcx, rdx, rbx, etc, not rax, rbx, rcx, rdx. --HG-- extra : convert_revision : 3abe6a723a6e30becfe34f8da707ea2ff5d4df77
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-28AtomicSimpleCPU: fix inadvertent loss of endian conversion on read.Steve Reinhardt
--HG-- extra : convert_revision : 367bf2431bf4f4eb7c4d5723816e5db6f7233aed
2007-07-27cache/memtest: fixes for functional accesses.Steve Reinhardt
--HG-- extra : convert_revision : 688ba4d882cad2c96cf44c9e46999f74266e02ee
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
--HG-- extra : convert_revision : e06a950964286604274fba81dcca362d75847233
2007-07-26X86: Fix argument register indexing.Gabe Black
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg. --HG-- extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-23Fix WriteReq/StoreCondReq setting in O3.Steve Reinhardt
--HG-- extra : convert_revision : b41571535f3d1f78df3cb6e48c16de5c7549d87f
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