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path: root/src/cpu
AgeCommit message (Expand)Author
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2015-05-05mem: Snoop into caches on uncacheable accessesAndreas Hansson
2015-05-05cpu: Work around gcc 4.9 issues with Num_OpClassesAndreas Hansson
2015-04-29cpu: o3: replace issueLatency with bool pipelinedNilay Vaish
2015-04-29cpu: o3: single cycle default div microop latency on x86Nilay Vaish
2015-04-22cpu: remove conditional check (count > 0) on o3 IQ squashesBrandon Potter
2015-04-20cpu: Remove the InOrderCPU from the treeAndreas Hansson
2015-04-14config, cpu: fix progress interval for switched CPUsMalek Musleh
2015-04-13cpu: re-organizes the branch predictor structure.Dibakar Gope
2015-04-03cpu: fix system total instructions accountingNikos Nikoleris
2015-03-26cpu: Fix InstPBTrace inheritanceAndreas Hansson
2015-03-23mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMWSteve Reinhardt
2015-03-19cpu: Fix TrafficGen message formatWendy Elsasser
2015-02-11mem: restructure Packet cmd initialization a bit moreSteve Reinhardt
2015-03-09cpu: o3: another assert instead of checkNilay Vaish
2015-03-09cpu: o3: Remove unused code in iew, add assert instead.Nilay Vaish
2015-03-09cpu: o3: commit: mark pipeline delay variable as constsNilay Vaish
2015-03-09cpu: o3: remove unused stat variables.Nilay Vaish
2015-03-09cpu: o3: combine if with same conditionNilay Vaish
2015-03-09cpu: o3: remove member variable squashCounterNilay Vaish
2015-03-09cpu: o3: remove unused function annotateMemoryUnits()Nilay Vaish
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-03-02arm: Share a port for the two table walker objectsAndreas Hansson
2015-03-02cpu: o3 register renaming request handling improvedRekai
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-03-02cpu: Add a PC-value to the traffic generator requestsStephan Diestelhorst
2015-02-16cpu: TrafficGen sinks snoops without complainingAndreas Hansson
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2015-02-16cpu: add support for outputing a protobuf formatted CPU traceAli Saidi
2015-02-11cpu: Tidy up the MemTest and make false sharing more obviousAndreas Hansson
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2015-02-06cpu: Idle CPU status logic revisedAlexandru Dutu
2015-02-03cpu: Ensure timing CPU sinks response before sending new requestAndreas Hansson
2015-01-25arm: always set the IsFirstMicroop flagAli Saidi
2015-01-25sim: Clean up InstRecordAli Saidi
2015-01-25cpu: Remove all notion that we know when the cpu is misspeculating.Ali Saidi
2015-01-25cpu: Put all CPU instruction tracers in a single fileAli Saidi
2015-01-25cpu: remove legion tracerAli Saidi
2015-01-22mem: Clean up Request initialisationAndreas Hansson
2015-01-20cpu: commit probe notification on every microop or macroopNikos Nikoleris
2015-01-20cpu: Fix retry bug in MinorCPU LSQAndreas Hansson
2015-01-10cpu: fix RetiredStores probe pointNikos Nikoleris
2015-01-03minor: fixed LSQ MasterPortIDAndrew Lukefahr
2014-12-09Let other objects set up memory like regions in a KVM VM.Gabe Black
2014-12-05cpu: Only check for PC events on instruction boundaries.Gabe Black
2014-12-02cpu: Fix retries on barrier/store in Minor's store bufferAndrew Bardsley
2014-12-02cpu: Fix memoryIssueLimit checking in MinorAndrew Bardsley
2014-12-02cpu, o3: Ignored invalidate causing same-address load reorderingMarco Elver
2014-12-02cpu: Move packet deallocation to recvTimingResp in the O3 CPUStephan Diestelhorst
2014-12-02mem: Assume all dynamic packet data is array allocatedAndreas Hansson
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