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path: root/src/cpu
AgeCommit message (Expand)Author
2011-02-04inorder: fault handlingKorey Sewell
2011-02-04inorder: pcstate and delay slots bugKorey Sewell
2011-02-04inorder: add a fetch buffer to fetch unitKorey Sewell
2011-02-04inorder: overload find-req fnKorey Sewell
2011-02-04inorder: implement separate fetch unitKorey Sewell
2011-02-04inorder: cache port blockingKorey Sewell
2011-02-04inorder: stage width as a python parameterKorey Sewell
2011-02-04inorder: multi-issue branch resolutionKorey Sewell
2011-02-04inorder: pipe. stage inst. bufferingKorey Sewell
2011-02-04inorder: change skidBuffer to list instead of queueKorey Sewell
2011-02-04inorder: activity tracking bugKorey Sewell
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-02-02O3: Fix a style bug in O3.Gabe Black
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
2011-01-18O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.Matt Horsnell
2011-01-18O3: Don't test misprediction on load instructions until executed.Matt Horsnell
2011-01-18O3: Keep around the last committed instruction and use for squashing.Ali Saidi
2011-01-18O3: Don't try to scoreboard misc registers.Ali Saidi
2011-01-18O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.Matt Horsnell
2011-01-18O3: Fix mispredicts from non control instructions.Matt Horsnell
2011-01-18O3: Fixes the way prefetches are handled inside the iew unit.Matt Horsnell
2011-01-18O3: Support timing translations for O3 CPU fetch.Ali Saidi
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2011-01-18O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.Min Kyu Jeong
2011-01-12inorder: fix RUBY_FS buildKorey Sewell
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2011-01-07inorder: replace schedEvent() code with reschedule().Steve Reinhardt
2011-01-07inorder: get rid of references to mainEventQueue.Steve Reinhardt
2011-01-03Move sched_list.hh and timebuf.hh from src/base to src/cpu.Steve Reinhardt
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
2010-12-22This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh f...Nilay Vaish
2010-12-21memtest: delete some crufty dead codeSteve Reinhardt
2010-12-20Style: Replace some tabs with spaces.Gabe Black
2010-12-07O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).Ali Saidi
2010-12-07O3: Support squashing all state after special instructionAli Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-12-07ARM: Support switchover with hardware table walkersAli Saidi
2010-12-01ruby: Converted old ruby debug calls to M5 debug callsNilay Vaish
2010-11-23X86: Loosen an assert for x86 and connect the APIC ports when caches are used.Gabe Black
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-18O3: Fix fp destination register flattening, and index offset adjusting.Gabe Black
2010-11-15O3: Make O3 support variably lengthed instructions.Gabe Black
2010-11-15O3: reset architetural state by calling clear()Ali Saidi
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15O3: prevent a squash when completeAcc() modifies misc reg through TC.Min Kyu Jeong
2010-11-15SCons: Cleanup SCons output during compileAli Saidi
2010-11-15CPU: Fix bug when a split transaction is issued to a faster cacheAli Saidi
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi