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2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. --HG-- extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-03-05Add x86 version of call to "decode"Gabe Black
--HG-- extra : convert_revision : bb799dcea58b51d6e1d3d744581ea48c5c1490fe
2007-03-05Added an x86 dyninstGabe Black
--HG-- extra : convert_revision : 2317e9bb0bcf8010ab5d02019f7a14eeb7b1459c
2007-03-03Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore --HG-- extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-03-02make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way ↵Ali Saidi
as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly --HG-- extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
2007-02-28Make trap instructions always generate TrapInstruction Fault objects which ↵Gabe Black
call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running. --HG-- extra : convert_revision : ea873f01c62234c0542f310cc143c6a7c76ade94
2007-02-17Give the progress event its own priorityNathan Binkert
--HG-- extra : convert_revision : 6357ade64deb42fae68b2766545b1c4cdc673fc9
2007-02-17Default to tracing being disabled in C++, it will be turnedNathan Binkert
on in python. Fix the trace start code so it actually starts when it is suppsed to. Make the Exec tracing stuff obey the trace enabled flag. --HG-- extra : convert_revision : 634ba0b4f52345d4bf40d43e239cef7ef43e7691
2007-02-13Merge all of the execution trace configuration stuff intoNathan Binkert
the traceflags infrastructure. InstExec is now just Exec and all of the command line options are now trace options. --HG-- extra : convert_revision : 4adfa9dfbb32622d30ef4e63c06c7d87da793c8f
2007-02-12some forgotten commitsAli Saidi
--HG-- extra : convert_revision : 213440066c700ed5891a6d4568928b7f3f2fe750
2007-02-12Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem src/cpu/simple/atomic.cc: merge steve's changes in. --HG-- extra : convert_revision : a17eda37cd63c9380af6fe68b0aef4b1e1974231
2007-02-12rename store conditional stuff as extra data so it can be used for ↵Ali Saidi
conditional swaps as well Add support for a twin 64 bit int load Add Memory barrier and write barrier flags as appropriate Make atomic memory ops atomic src/arch/alpha/isa/mem.isa: src/arch/alpha/locked_mem.hh: src/cpu/base_dyn_inst.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: rename store conditional stuff as extra data so it can be used for conditional swaps as well src/arch/alpha/types.hh: src/arch/mips/types.hh: src/arch/sparc/types.hh: add a largest read data type for statically allocating read buffers in atomic simple cpu src/arch/isa_parser.py: Add support for a twin 64 bit int load src/arch/sparc/isa/decoder.isa: Make atomic memory ops atomic Add Memory barrier and write barrier flags as appropriate src/arch/sparc/isa/formats/mem/basicmem.isa: add post access code block and define a twinload format for twin loads src/arch/sparc/isa/formats/mem/blockmem.isa: remove old microcoded twin load coad src/arch/sparc/isa/formats/mem/mem.isa: swap.isa replaces the code in loadstore.isa src/arch/sparc/isa/formats/mem/util.isa: add a post access code block src/arch/sparc/isa/includes.isa: need bigint.hh for Twin64_t src/arch/sparc/isa/operands.isa: add a twin 64 int type src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: add support for twinloads add support for swap and conditional swap instructions rename store conditional stuff as extra data so it can be used for conditional swaps as well src/mem/packet.cc: src/mem/packet.hh: Add support for atomic swap memory commands src/mem/packet_access.hh: Add endian conversion function for Twin64_t type src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: Add support for atomic swap memory commands Rename sc code to extradata --HG-- extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
2007-02-12Merge zizzer.eecs.umich.edu:/bk/newmemSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-head --HG-- extra : convert_revision : 496428e23050122a8a0029e5fddea261bef5729e
2007-02-12Move store conditional result checking from SimpleAtomicCpu writeSteve Reinhardt
function into Alpha ISA description. write now just generically returns a result value if the res pointer is non-null (which means we can only provide a res pointer if we expect a valid result value). --HG-- extra : convert_revision : fb1c315515787f5fbbf7d1af7e428bdbfe8148b8
2007-02-10Clean up tracing stuff more, get rid of the trace log sinceNathan Binkert
its not all that useful. Fix a few bugs with python/C++ integration. --HG-- extra : convert_revision : a706512f7dc8b0c88f1ff96fe35ab8fbf9548b78
2007-02-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head --HG-- extra : convert_revision : c56b8160b403fde235636ca5b5b4cecd206ffa4c
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
Created MemCmd class to wrap enum and provide handy methods to check attributes, convert to string/int, etc. --HG-- extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-02-06more fp fixesAli Saidi
fix unaligned accesses in mmaped disk device src/arch/sparc/isa/decoder.isa: get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code src/arch/sparc/isa/formats/basic.isa: move the cexec into the aexec field src/cpu/exetrace.cc: copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer src/dev/sparc/mm_disk.cc: src/dev/sparc/mm_disk.hh: fix unaligned accesses in the memory mapped disk device --HG-- extra : convert_revision : aaa33096b08cf0563fe291d984a87493a117e528
2007-02-02fix mostly floating point relatedAli Saidi
src/arch/sparc/floatregfile.cc: fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them src/arch/sparc/isa/decoder.isa: fix some fp implementations src/arch/sparc/isa/formats/basic.isa: add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op src/arch/sparc/isa/includes.isa: include the appropriate header files for the rounding code src/arch/sparc/miscregfile.cc: print fsr out when it's read/written and the Sparc traceflgas in on src/cpu/exetrace.cc: fix printing of float registers --HG-- extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
2007-01-30add fsr to the list of registers we are interested inAli Saidi
--HG-- extra : convert_revision : 2cc0d0144abab264aa0ec8c07242cdab2dffd4f8
2007-01-30Make SPARC checkpointing workAli Saidi
src/arch/sparc/floatregfile.cc: Fix serialization for fpreg src/arch/sparc/intregfile.cc: fix serialization for intreg src/arch/sparc/miscregfile.cc: fix serialization from miscreg src/arch/sparc/pagetable.cc: fix serialization for page table src/arch/sparc/regfile.cc: need to serialize nnpc src/arch/sparc/tlb.cc: write serialization code for tlb src/cpu/base.cc: provide a way to find the thread number a context is serialize the instruction counter src/cpu/base.hh: provide a way to find the thread number a context is and given a thread number find a context pointer src/cpu/cpuevent.hh: provide method to get thread context from a cpu event for serialization src/dev/sparc/t1000.cc: src/dev/sparc/t1000.hh: nothing to serialize in t1000 src/sim/serialize.cc: src/sim/serialize.hh: Make findObj() work (it hasn't since we did the python conversion stuff) --HG-- extra : convert_revision : a95bc4e3c3354304171efbe3797556fdb146bea2
2007-01-29fix some over sights in moving windowing and ccr registers to int reg fileAli Saidi
--HG-- extra : convert_revision : 4e83e5163076aeef72ec5caf1e0d7adea11da875
2007-01-29Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 7b8b791815d1fb51cc7ad085307a640b2ee51642
2007-01-29A minor hack to get branch prediction to behave like before on Alpha.Gabe Black
--HG-- extra : convert_revision : 1eaabd13c72aa42c512a04d162a87491818bc621
2007-01-29Fixed a warning about an unused variable.Gabe Black
--HG-- extra : convert_revision : f9c78e86b60c3085cd95b1b4e132205e0ef584dd
2007-01-28fix comparing fp registers between legion and m5Ali Saidi
make fp writes also chatty with the Sparc traceflag src/arch/sparc/floatregfile.cc: make fp writes also chatty with the Sparc traceflag src/cpu/exetrace.cc: fix comparing fp registers between legion and m5 --HG-- extra : convert_revision : f3703afae56249f137451262bc1b6919d465e714
2007-01-28Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 2398e48722dd71ddf270e93bd7b387078fb30e6b
2007-01-27While I'm waiting for legion to run make m5 compile with a few more compilersAli Saidi
SConstruct: src/SConscript: Add flags for Intel CC while i'm at it src/base/compiler.hh: the _Pragma stuff needst to be called this way unless someone happens to have a cleaner way src/base/cprintf_formats.hh: add std:: where appropriate src/base/statistics.hh: use this->map since icc was getting confused about std::map vs the locally defined map src/cpu/static_inst.hh: Add some more dummy returns where needed src/mem/packet.hh: add more dummy returns where needed src/sim/host.hh: use limits to come up with max tick --HG-- extra : convert_revision : 08e9f7898b29fb9d063136529afb9b6abceab60c
2007-01-27Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa_traits.hh: src/arch/sparc/system.cc: Hand Merge --HG-- extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c
2007-01-26Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 53ee81b099930d4d827db99e2d944ffb8645c706
2007-01-26Make Sparc traceflag even more chattyAli Saidi
some fixes to fp instructions to use the single precision registers if this is an fp op emit fp check code add fpregs to m5legion struct src/arch/sparc/floatregfile.cc: Make Sparc traceflag even more chatty src/arch/sparc/isa/base.isa: add code to check if the fpu is enabled src/arch/sparc/isa/decoder.isa: some fixes to fp instructions to use the single precision registers fix smul again fix subc/subcc/subccc condition code setting src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/mem/util.isa: if this is an fp op emit fp check code src/cpu/exetrace.cc: check fp regs as well as int regs src/cpu/m5legion_interface.h: add fpregs to m5legion struct --HG-- extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232
2007-01-26Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.suncc --HG-- extra : convert_revision : 1706f6218abec7eb575dcff3ad4aef83894f64ab
2007-01-26Merge zeep.pool:/z/saidi/work/m5.newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.suncc --HG-- extra : convert_revision : 20f61a524a3b53fc0afcf53a24b5a1fe1d96f579
2007-01-26make our code a little more standards compliantAli Saidi
pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-26Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5 --HG-- extra : convert_revision : 1b854ec7caa33d3009383754206b643494c4c42d
2007-01-26eliminate cpu checkInterrupts bool, it is redundant and unnecessary.Lisa Hsu
--HG-- extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
2007-01-25fix smul and sdiv to sign extend, and handle overflow/underflow corretlyAli Saidi
Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back src/arch/sparc/isa/decoder.isa: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/formats/mem/blockmem.isa: Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/includes.isa: Use limits for 32bit underflow/overflow detection src/arch/sparc/tlb.cc: only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync src/arch/sparc/tlb_map.hh: add a print function to dump the tlb lookup table src/cpu/simple/base.cc: if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back --HG-- extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4
2007-01-24Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 2d7ae62a59b91d735bbac093f8a4ab542ea75eee
2007-01-23use pstate.am to mask off PC/NPC where it needs to +beAli Saidi
check writability of tlb cache entry before using update tagaccess in places I forgot to move the tlb privileged test up since it is higher priority src/arch/sparc/faults.cc: save only 32 bits of PC/NPC if Pstate.am is set src/arch/sparc/isa/decoder.isa: return only 32 bits of PC/NPC if Pstate.am is set increment cleanwin correctly src/arch/sparc/tlb.cc: check writability of cache entry update tagaccess in a few more places move the privileged test up since it is higher priority src/cpu/exetrace.cc: mask off upper bits of pc if pstate.am is set before comparing to legion --HG-- extra : convert_revision : 02a51c141ee3f9a2600c28eac018ea7216f3655c
2007-01-22Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmemo3 src/sim/byteswap.hh: Hand Merge --HG-- extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8
2007-01-19Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5 --HG-- extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376
2007-01-16In the case that we generate a fault (e.g. a tlb miss) on a microcoded ↵Ali Saidi
instruction set curMacroStaticInst to null This way we'll jump immediately to the handler --HG-- extra : convert_revision : 36218d3a5c2342337e66e1229ea2219533efd41e
2007-01-16Fix legion lock code a bit so that if we jump out of a micro coded ↵Ali Saidi
instruction (because of a fault on the first op) we don't lose sync with legion Only print TLB if there is a tlb difference --HG-- extra : convert_revision : f3baf667ca466d6b8efcaccd186ecec14498229d
2007-01-16Modify ISA and staticInst to support a IsFirstMicroOp flagAli Saidi
Increment instruction count on first micro-op instead of last src/arch/sparc/isa/decoder.isa: Implement a twin load for ASI_LDTX_P(0xe2) src/arch/sparc/isa/formats/mem/blockmem.isa: set the new flag IsFirstMicroOp when needed src/cpu/simple/atomic.cc: Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion) src/cpu/static_inst.hh: Add IsFirstMicroop flag to static insts --HG-- extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc
2007-01-08the way i understand it, interrupts in m5 is a little bloated. the usage of ↵Lisa Hsu
CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in. src/arch/sparc/interrupts.hh: fill in how we do interrupts on sparc a little bit. 1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU. 2) fill in getInterrupts() a little bit. also, update the bitfield access to be HPSTATE::hpriv, etc. src/arch/sparc/ua2005.cc: 1) update formatting 2) change the way interrupts are done to use the new way to tickle the CPU. src/cpu/base.cc: src/cpu/base.hh: overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value. --HG-- extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
2007-01-08change when legion-lock causes the simulation to die. It now happens after ↵Ali Saidi
two consuctive differences since we compare stuff at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early. --HG-- extra : convert_revision : f237363eababb2aad67e5b41670cf40be048a042
2007-01-03FormattingNathan Binkert
--HG-- extra : convert_revision : bf1eae73995f772a4343c8ebcb254818eeb5d949
2007-01-03Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : f4a05accb8fa24d425dd818b1b7f268378180e99
2006-12-30Fix up previous commit to proper logic.Kevin Lim
src/cpu/o3/commit_impl.hh: Oops, changed the logic a little bit. Fix it up to how it used to be. --HG-- extra : convert_revision : df7f69b0997207b611374c3c92880f3a405e88be
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