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AgeCommit message (Expand)Author
2011-02-23O3: If there is an outstanding table walk don't let the inst queue sleep.Ali Saidi
2011-02-23ARM: Do something for ISB, DSB, DMBAli Saidi
2011-02-23ARM: Fix bug that let two table walks occur in parallel.Ali Saidi
2011-02-23O3: Fix bug when a squash occurs right before TLB miss returns.Ali Saidi
2011-02-18m5: merge inorder/release-notes/make_release changesKorey Sewell
2011-02-18inorder: add names and slot #s to res. dprintsKorey Sewell
2011-02-18inorder: ignore nops in execution unitKorey Sewell
2011-02-18inorder: update graduation unitKorey Sewell
2011-02-18inorder: recognize isSerializeAfter flagKorey Sewell
2011-02-18inorder: update default thread size(=1)Korey Sewell
2011-02-18inorder: don't overuse getLatency()Korey Sewell
2011-02-18inorder: update max. resource bandwidthsKorey Sewell
2011-02-18inorder: cleanup in destructorsKorey Sewell
2011-02-18inorder: fix cache/fetch unit memory leaksKorey Sewell
2011-02-18inorder: remove events for zero-cycle resourcesKorey Sewell
2011-02-18inorder: update pipeline interface for handling finished resource reqsKorey Sewell
2011-02-18inorder: remove request map, use request vectorKorey Sewell
2011-02-18inorder: add valid bit for resource requestsKorey Sewell
2011-02-18inorder: remove reqRemoveListKorey Sewell
2011-02-18inorder: initialize res. req. vectors based on resource bandwidthKorey Sewell
2011-02-13O3: Fetch from the microcode ROM when needed.Gabe Black
2011-02-13O3: Fix GCC 4.2.4 complaintAli Saidi
2011-02-12inorder: clean up the old way of inst. schedulingKorey Sewell
2011-02-12inorder: utilize cached skeds in pipelineKorey Sewell
2011-02-12inorder: define iterator for resource schedulesKorey Sewell
2011-02-12inorder: stage scheduler for front/back end schedule creationKorey Sewell
2011-02-12inorder: cache instruction schedulesKorey Sewell
2011-02-12inorder: comments for resource sked classKorey Sewell
2011-02-12inorder: remove unused fileKorey Sewell
2011-02-11O3: Fix pipeline restart when a table walk completes in the fetch stage.Giacomo Gabrielli
2011-02-11SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk o...Ali Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06TimingSimpleCPU: split data sender state fixJoel Hestness
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
2011-02-04inorder: fault handlingKorey Sewell
2011-02-04inorder: pcstate and delay slots bugKorey Sewell
2011-02-04inorder: add a fetch buffer to fetch unitKorey Sewell
2011-02-04inorder: overload find-req fnKorey Sewell
2011-02-04inorder: implement separate fetch unitKorey Sewell
2011-02-04inorder: cache port blockingKorey Sewell
2011-02-04inorder: stage width as a python parameterKorey Sewell
2011-02-04inorder: multi-issue branch resolutionKorey Sewell
2011-02-04inorder: pipe. stage inst. bufferingKorey Sewell
2011-02-04inorder: change skidBuffer to list instead of queueKorey Sewell
2011-02-04inorder: activity tracking bugKorey Sewell
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-02-02O3: Fix a style bug in O3.Gabe Black
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black