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path: root/src/cpu
AgeCommit message (Expand)Author
2011-01-03Move sched_list.hh and timebuf.hh from src/base to src/cpu.Steve Reinhardt
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
2010-12-22This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh f...Nilay Vaish
2010-12-21memtest: delete some crufty dead codeSteve Reinhardt
2010-12-20Style: Replace some tabs with spaces.Gabe Black
2010-12-07O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).Ali Saidi
2010-12-07O3: Support squashing all state after special instructionAli Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-12-07ARM: Support switchover with hardware table walkersAli Saidi
2010-12-01ruby: Converted old ruby debug calls to M5 debug callsNilay Vaish
2010-11-23X86: Loosen an assert for x86 and connect the APIC ports when caches are used.Gabe Black
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-18O3: Fix fp destination register flattening, and index offset adjusting.Gabe Black
2010-11-15O3: Make O3 support variably lengthed instructions.Gabe Black
2010-11-15O3: reset architetural state by calling clear()Ali Saidi
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15O3: prevent a squash when completeAcc() modifies misc reg through TC.Min Kyu Jeong
2010-11-15SCons: Cleanup SCons output during compileAli Saidi
2010-11-15CPU: Fix bug when a split transaction is issued to a faster cacheAli Saidi
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-11-08ARM: Make all ARM uops delayed commit.Ali Saidi
2010-11-08sim: Use forward declarations for ports.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-10-24O3: Get rid of a bunch of commented out lines.Gabe Black
2010-10-04Alpha: Fix Alpha NumMiscArchRegs constant.Gabe Black
2010-09-30CPU/Cache: Fix some errors exposed by valgrindAli Saidi
2010-09-20CPU: Fix O3 and possible InOrder segfaults in FS.Gabe Black
2010-09-14CPU: Trim unnecessary includes from some common files.Gabe Black
2010-09-13CPU: Get rid of the now unnecessary getInst/setInst family of functions.Gabe Black
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2010-08-31CPU: Get rid of the unused ev5_trap function on the simple and checker CPUs.Gabe Black
2010-08-25memtest: fix/cleanup functional access testingSteve Reinhardt
2010-08-25CPU: Print out traces for faluting inst when the flag ExecFaulting is setAli Saidi
2010-08-25ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)Min Kyu Jeong
2010-08-24testers: move testers to a new directoryBrad Beckmann
2010-08-23ISA: Get rid of old, unused utility functions cluttering up the ISAs.Gabe Black
2010-08-23CPU: Make the constants for StaticInst flags visible outside the class.Gabe Black
2010-08-23O3: Skipping mem-order violation check for uncachable loads.Min Kyu Jeong
2010-08-23ARM: Improve printing of uop disassembly.Min Kyu Jeong
2010-08-23CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflagMin Kyu Jeong
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory instru...Min Kyu Jeong
2010-08-23ARM: mark msr/mrs instructions as SerializeBefore/AfterMin Kyu Jeong
2010-08-23O3: Handle loads when the destination is the PC.Min Kyu Jeong
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
2010-08-23CPU: Set a default value when readBytes faults.Ali Saidi
2010-08-20ruby: Fixed minor bug in ruby test for setting the request typeBrad Beckmann
2010-08-20ruby: Resurrected Ruby's deterministic testsBrad Beckmann
2010-08-20memtest: Memtester support for DMABrad Beckmann