summaryrefslogtreecommitdiff
path: root/src/cpu
AgeCommit message (Expand)Author
2007-10-02Predecoder: Clear out predecoder state on an ITLB fault.Gabe Black
2007-09-25Merge with head.Gabe Black
2007-09-25SPARC: Fix a stupid mistake which was breaking the SPARC regressions.Gabe Black
2007-09-24X86: Get X86_FS to compile.Gabe Black
2007-09-19X86: Put in the foundation for x87 stack based fp registers.Gabe Black
2007-09-04X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actua...Gabe Black
2007-08-31X86: Get x86 to compile again after the simobject constructor change.Gabe Black
2007-08-30Fix miscellaneous small typos.Miles Kaufmann
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-08-26Merge with headGabe Black
2007-08-26O3 CPU: Remove alignment check from dynamic instruction read/write functions.Gabe Black
2007-08-26Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.Gabe Black
2007-08-26Simple CPU: Added code that will split requests that cross block boundaries i...Gabe Black
2007-08-26Simple CPU: Make sure only instructions which complete without faulting are c...Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-08-21Merge with head.Gabe Black
2007-08-21o3: Fix for retry ID bug.Kevin Lim
2007-08-13O3: Set up the predicted npc and nnpc for a fault carrying noop so that it do...Gabe Black
2007-08-13Move the "translate" member functions back into the base o3 class.Gabe Black
2007-08-08Added fastmem option.Vincentius Robby
2007-08-08Port, StaticInst: Revert unnecessary changes.Vincentius Robby
2007-08-08alpha: Make the TLB cache to actually work.Vincentius Robby
2007-08-07Merge with head.Gabe Black
2007-08-07X86: Make a microcode branch microop.Gabe Black
2007-08-04switching: turn on profiling after a switch if there's an eventNathan Binkert
2007-08-04SimpleCPU: Add some DPRINTFsNathan Binkert
2007-08-04StaticInst: Fix decode cache initialization. Cache functionality was negated.Vincentius Robby
2007-08-01Merge with head.Gabe Black
2007-08-01X86: Reorganize the native tracing code.Gabe Black
2007-07-31Add a flag to indicate an instruction triggers a syscall in SE mode.Gabe Black
2007-07-31Merge from head.Steve Reinhardt
2007-07-30Fix problem with tracer not being initialized.Gabe Black
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
2007-07-29BsaeCPU: Get rid of some bad DPRINTFs.Steve Reinhardt
2007-07-29X86: Fix register ordering.Gabe Black
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-07-28AtomicSimpleCPU: fix inadvertent loss of endian conversion on read.Steve Reinhardt
2007-07-27cache/memtest: fixes for functional accesses.Steve Reinhardt
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-26X86: Fix argument register indexing.Gabe Black
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-07-23Fix WriteReq/StoreCondReq setting in O3.Steve Reinhardt
2007-07-15Fix bug with timing snoop upcalls to MemTest object.Steve Reinhardt
2007-07-15Fix up a bunch of multilevel coherence issues.Steve Reinhardt
2007-07-15Fix problem with unset max_loads in memtest.Steve Reinhardt
2007-07-02Couple more minor bug fixes for FS timing mode.Steve Reinhardt
2007-07-02Fix a couple LL/SC bugs that only affected timing mode.Steve Reinhardt
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 04:29:39 +0000