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cpu
Age
Commit message (
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Author
2007-08-08
Added fastmem option.
Vincentius Robby
2007-08-08
Port, StaticInst: Revert unnecessary changes.
Vincentius Robby
2007-08-08
alpha: Make the TLB cache to actually work.
Vincentius Robby
2007-08-07
Merge with head.
Gabe Black
2007-08-07
X86: Make a microcode branch microop.
Gabe Black
2007-08-04
switching: turn on profiling after a switch if there's an event
Nathan Binkert
2007-08-04
SimpleCPU: Add some DPRINTFs
Nathan Binkert
2007-08-04
StaticInst: Fix decode cache initialization. Cache functionality was negated.
Vincentius Robby
2007-08-01
Merge with head.
Gabe Black
2007-08-01
X86: Reorganize the native tracing code.
Gabe Black
2007-07-31
Add a flag to indicate an instruction triggers a syscall in SE mode.
Gabe Black
2007-07-31
Merge from head.
Steve Reinhardt
2007-07-30
Fix problem with tracer not being initialized.
Gabe Black
2007-07-29
Merge Gabe's changes from head.
Steve Reinhardt
2007-07-29
BsaeCPU: Get rid of some bad DPRINTFs.
Steve Reinhardt
2007-07-29
X86: Fix register ordering.
Gabe Black
2007-07-28
Turn the instruction tracing code into pluggable sim objects.
Gabe Black
2007-07-28
AtomicSimpleCPU: fix inadvertent loss of endian conversion on read.
Steve Reinhardt
2007-07-27
cache/memtest: fixes for functional accesses.
Steve Reinhardt
2007-07-26
Merge python and x86 changes with cache branch
Nathan Binkert
2007-07-26
X86: Fix argument register indexing.
Gabe Black
2007-07-23
Major changes to how SimObjects are created and initialized. Almost all
Nathan Binkert
2007-07-23
Fix WriteReq/StoreCondReq setting in O3.
Steve Reinhardt
2007-07-15
Fix bug with timing snoop upcalls to MemTest object.
Steve Reinhardt
2007-07-15
Fix up a bunch of multilevel coherence issues.
Steve Reinhardt
2007-07-15
Fix problem with unset max_loads in memtest.
Steve Reinhardt
2007-07-02
Couple more minor bug fixes for FS timing mode.
Steve Reinhardt
2007-07-02
Fix a couple LL/SC bugs that only affected timing mode.
Steve Reinhardt
2007-06-30
Make CPU models use new LoadLockedReq/StoreCondReq commands.
Steve Reinhardt
2007-06-30
Event descriptions should not end in "event"
Steve Reinhardt
2007-06-30
Get rid of Packet result field. Error responses are
Steve Reinhardt
2007-06-28
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2007-06-28
o3cpu build for mips
Korey Sewell
2007-06-23
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2007-06-23
Minor fix plus new assertion to catch similar bugs.
Steve Reinhardt
2007-06-22
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2007-06-22
mips import pt. 1
Korey Sewell
2007-06-21
Merge zizzer.eecs.umich.edu:/bk/newmem
Gabe Black
2007-06-21
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2007-06-21
Getting closer...
Steve Reinhardt
2007-06-20
Fix compiler errors.
Gabe Black
2007-06-20
Removed "adding instead of dividing" trick.
Vincentius Robby
2007-06-20
Don't do checker stuff if the checker is not defined
Nathan Binkert
2007-06-20
Make sure all parameters have default values if they're
Nathan Binkert
2007-06-19
Merge zizzer.eecs.umich.edu:/bk/newmem
Gabe Black
2007-06-19
Missed an "offset" to get rid of.
Gabe Black
2007-06-19
Make branches work by repopulating the predecoder every time through. This is...
Gabe Black
2007-06-18
fix bug in timing cpu. getTime() is the time the requset was created, not the...
Ali Saidi
2007-06-17
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2007-06-17
More major reorg of cache. Seems to work for atomic mode now,
Steve Reinhardt
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