| Age | Commit message (Expand) | Author |
|---|
| 2017-11-29 | cpu: Don't override ISA if provided by user | Andreas Sandberg |
| 2017-11-29 | cpu-minor: Add missing instruction stats | David Guillen Fandos |
| 2017-11-28 | cpu-o3: Add missing vector stat initializers | Andreas Sandberg |
| 2017-11-21 | cpu, cpu, sim: move Cycle probe update | Jose Marinho |
| 2017-11-21 | cpu-o3: Prevent cpu from suspending if it is already draining | Nikos Nikoleris |
| 2017-11-20 | cpu: Make automatic transition to OFF optional | Jose Marinho |
| 2017-11-20 | pwr: Adds logic to enter power gating for the cpu model | Anouk Van Laer |
| 2017-11-14 | cpu, probe: Fix elastic trace register dependency | Radhika Jagtap |
| 2017-10-19 | cpu-o3: Add M5_VAR_USED to variable | Jason Lowe-Power |
| 2017-10-13 | cpu-o3: Check predication before the SQ size for a debug print | Nikos Nikoleris |
| 2017-10-13 | cpu-o3: Avoid early checker verification for store conditionals | Nikos Nikoleris |
| 2017-09-11 | stats: Get rid of some kernel stats related cruft. | Gabe Black |
| 2017-09-06 | cpu: Fix bi-mode branch predictor thresholds | Rico Amslinger |
| 2017-09-01 | cpu-minor: Fix for addr range coverage calculation | Pau Cabre |
| 2017-08-30 | cpu-o3: fix data pkt initialization for split load | Matthias Hille |
| 2017-08-01 | kvm: Add a helper method to access device event queues | Andreas Sandberg |
| 2017-08-01 | cpu, kvm: Fix deadlock issue when resuming a drained system | Andreas Sandberg |
| 2017-07-19 | cpu: Add missing rename of vector registers in the O3 CPU | Rekai Gonzalez-Alberquilla |
| 2017-07-17 | cpu,o3: Fixed checkpointing bug occuring in the o3 CPU | Anouk Van Laer |
| 2017-07-12 | testers: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | kvm, mem: Refactor some Event subclasses into lambdas | Sean Wilson |
| 2017-07-12 | cpu: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | cpu, sim: Add param to force CPUs to wait for GDB | Jose Marinho |
| 2017-07-07 | kvm, arm: Don't forward IRQ/FIQ when using the kernel's GIC | Andreas Sandberg |
| 2017-07-05 | arch: ISA parser additions of vector registers | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Result refactoring | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Physical register structural + flat indexing | Nathanael Premillieu |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2017-06-20 | cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
| 2017-05-15 | cpu: fix problem with forwarding and locked load | Alec Roelke |
| 2017-05-02 | python: Use PyBind11 instead of SWIG for Python wrappers | Andreas Sandberg |
| 2017-04-03 | arm, kvm: implement GIC state transfer | Curtis Dunham |
| 2017-03-16 | cpu: Print progress messages in Trace CPU | Radhika Jagtap |
| 2017-02-27 | syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess s... | Brandon Potter |
| 2015-07-20 | syscall_emul: [patch 13/22] add system call retry capability | Brandon Potter |
| 2017-02-14 | sim, kvm: make KvmVM a System parameter | Curtis Dunham |
| 2016-11-09 | style: [patch 3/22] reduce include dependencies in some headers | Brandon Potter |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2017-01-03 | sim: Remove redundant export_method_cxx_predecls | Andreas Sandberg |
| 2016-12-21 | cpu: implement an L-TAGE branch predictor | Arthur Perais |
| 2016-12-21 | cpu: disallow speculative update of branch predictor tables (o3) | Arthur Perais |
| 2016-12-21 | cpu: correct comments in tournament branch predictor | Arthur Perais |
| 2016-12-21 | cpu: Resolve targets of predicted 'taken' decode for O3 | Arthur Perais |
| 2016-12-21 | cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3 | Arthur Perais |
| 2016-12-05 | cpu: Change traffic generators to use different values for writes | Nikos Nikoleris |
| 2016-11-30 | arch: [Patch 1/5] Added RISC-V base instruction set RV64I | Alec Roelke |
| 2016-11-30 | cpu: Remove branch predictor function predictInOrder | Jason Lowe-Power |
| 2016-10-15 | cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass | Fernando Endo |
