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path: root/src/cpu
AgeCommit message (Expand)Author
2016-02-06style: remove trailing whitespaceSteve Reinhardt
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
2016-01-17cpu: remove unnecessary data ptr from O3 internal read() funcsSteve Reinhardt
2016-01-11scons: Enable -Wextra by defaultAndreas Hansson
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-07-20ruby: more flexible ruby tester supportBrad Beckmann
2015-12-07cpu: Support virtual addr in elastic tracesRadhika Jagtap
2015-12-07cpu: Create record type enum for elastic tracesRadhika Jagtap
2015-12-07cpu: Add TraceCPU to playback elastic tracesRadhika Jagtap
2015-12-07proto, probe: Add elastic trace probe to o3 cpuRadhika Jagtap
2015-12-07probe: Add probe in Fetch, IEW, Rename and CommitRadhika Jagtap
2015-12-04cpu: fix unitialized variable which may cause assertion failurePau Cabre
2015-11-22cpu: Fix base FP and CC register index in o3 insertThread()Nathanael Premillieu
2015-11-22cpu: Fix memory leak in traffic generatorAndreas Hansson
2015-11-20cpu: Enforce 1 interrupt controller per threadAndreas Sandberg
2015-11-16o3: drop unused statistic wbPenalized and wbPenalizedRateNilay Vaish
2015-10-12misc: Add explicit overrides and fix other clang >= 3.5 issuesAndreas Hansson
2015-10-12misc: Remove redundant compiler-specific definesAndreas Hansson
2015-10-09isa: Add parameter to pick different decoder inside ISARekai Gonzalez Alberquilla
2015-10-06sim: add ExecMacro to Exec* compound debug flagsSteve Reinhardt
2015-09-30base: remove Trace::enabled flagCurtis Dunham
2015-09-30cpu,isa,mem: Add per-thread wakeup logicMitch Hayenga
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-09-30config,cpu: Add SMT support to Atomic and Timing CPUsMitch Hayenga
2015-09-30cpu: Change thread assignments for heterogenous SMTMitch Hayenga
2015-09-15cpu: pred: Local Predictor Reset in Tournament PredictorAndrew Lukefahr
2015-09-15cpu, o3: consider split requests for LSQ checksnoop operationsHongil Yoon
2015-08-29ruby: eliminate type uint64 and int64Nilay Vaish
2015-08-21mem: Reflect that packet address and size are always validAndreas Hansson
2015-08-21cpu: Move invldPid constant from Request to BaseCPUAndreas Hansson
2015-08-19ruby: reverts to changeset: bf82f1f7b040Nilay Vaish
2015-08-14ruby: eliminate type uint64 and int64Nilay Vaish
2015-08-14ruby: replace Address by AddrNilay Vaish
2015-08-11ruby: drop some redundant includesNilay Vaish
2015-08-07base: Declare a type for context IDsAndreas Sandberg
2015-07-20cpu: Fixed a bug on where to fetch the next instruction fromDavid Hashe
2015-07-31cpu: Update debug message from Fetch1 isDrained() in MinorAndreas Sandberg
2015-07-31cpu: Fix Minor drain issues when switched outAndreas Sandberg
2015-07-30cpu: Only activate thread 0 in Minor if the CPU is activeAndreas Sandberg
2015-07-30cpu: Fix drain issues in the Minor CPUAndreas Sandberg
2015-07-30cpu: Fix issue identified by UBSanAndreas Hansson
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-26cpu: o3: slight correction to identation in rename_impl.hhNilay Vaish
2015-07-10ruby: replace global g_abs_controls with per-RubySystem varBrandon Potter
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-07-04o3: correct the number of cc registers in rename mapNilay Vaish
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